原创 串行外设接口（SPI） cpld 被动接收

//---------------------------------------------------------------------
//    串行外设接口（SPI）   cpld 被动接收

//在下降沿 采集数据并发送数据 1BYTE

//要求mcu在末端采集数据。并在下降沿之前准备好数据。

module cpld_spi(
   clk,rst_n,
   mcu_sck,mcu_sdo,mcu_sdi,
   //set_I//,set_T,
   led1_data,led2_data
   
  );
input clk;  //50MHz
input rst_n; //低电平复位信号
input mcu_sck;
input mcu_sdo;
output mcu_sdi;
//input[15:0]  set_I;
//input[7:0]  set_T;
output[3:0] led1_data;
output[3:0] led2_data;
//**********************************************************************************

reg SPI_SCK0,SPI_SCK1,SPI_SCK2,SPI_SCK3; //接收数据寄存器，滤波用
wire neg_SPI_SCK; //表示数据线接收到下降沿

always @ (posedge clk or negedge rst_n) begin
 if(!rst_n) begin
   SPI_SCK0 <= 1'b0;
   SPI_SCK1 <= 1'b0;
   SPI_SCK2 <= 1'b0;
   SPI_SCK3 <= 1'b0;
  end
 else begin
   SPI_SCK0 <= mcu_sck;
   SPI_SCK1 <= SPI_SCK0;
   SPI_SCK2 <= SPI_SCK1;
   SPI_SCK3 <= SPI_SCK2;
  end
    end  
assign neg_SPI_SCK = SPI_SCK3 & SPI_SCK2 & ~SPI_SCK1 & ~SPI_SCK0; //接收到下降沿后neg_SPI_SCK置高一个时钟周期  
//**********************************************************************************  

reg[5:0] num;
reg mcu_sdi_r; 
reg [7:0]  set_I_r;
reg[3:0] led1_data_r,led2_data_r;

//--------------------------------------------------- 

always @ (posedge clk or negedge rst_n)begin
 if(!rst_n) begin
   num <= 6'd0;
   mcu_sdi_r <= 0;
   set_I_r <= 8'h56;
   led1_data_r <= 4'd0;
      led2_data_r  <= 4'd0;
   
   end  
     else if (neg_SPI_SCK) begin     // cpld
         num <= num+1'b1;
         
         
             case (num)
              6'd0: led1_data_r[3] <= mcu_sdo;
              6'd1: led1_data_r[2] <= mcu_sdo;
              6'd2: led1_data_r[1] <= mcu_sdo;
              6'd3: led1_data_r[0] <= mcu_sdo;
              6'd4: led2_data_r[3] <= mcu_sdo;
              6'd5: led2_data_r[2] <= mcu_sdo;
              6'd6: led2_data_r[1] <= mcu_sdo;
              6'd7: begin
                    led2_data_r[0] <= mcu_sdo;
                           num <= 6'd0;
                     end
               default: ;
     endcase
           
         
             case (num)
      6'd0: mcu_sdi_r <= set_I_r[7]; //锁存第0bit
      6'd1: mcu_sdi_r <= set_I_r[6]; //锁存第1bit
      6'd2: mcu_sdi_r <= set_I_r[5]; //锁存第2bit
      6'd3: mcu_sdi_r <= set_I_r[4]; //锁存第3bit
      6'd4: mcu_sdi_r <= set_I_r[3]; //锁存第4bit
      6'd5: mcu_sdi_r <= set_I_r[2]; //锁存第5bit
      6'd6: mcu_sdi_r <= set_I_r[1]; //锁存第6bit
      6'd7: begin
            mcu_sdi_r <= set_I_r[0]; //锁存第7bit
             
               end
      default:num <= 6'd0;
     endcase
    
   end
 end
assign mcu_sdi = mcu_sdi_r; 
assign led1_data = led1_data_r;
assign led2_data = led2_data_r;

endmodule