PMC<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />9840A+PMC5180A PMC信号输入输出系统解决方案<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
用于软件无线电收发系统输入输出PMC板卡由3部分组成:ADC输入板卡(PMC9840A),DAC输出板卡(PMC5180A)和PMC载板组成(用户自定义)。系统组成框图如下所示:
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Specifications:
ANALOG INPUTS
No. of Analog Input Channels: 2
Analog Connector Type: SMA Coaxial, transformer coupled
Input Impedance: 50 Ohm
Full Scale Rx Input: ±1Vpp
Max. ADC Sampling Rate: 105 MHz/ch. (simultaneous)
Input Transformer Bandwidth: 2 MHz – 775 MHz (-3 dB point)
6 MHz – 250 MHz (-1 dB point)
Max ADC Sampling Rate : 105 MHz/ch (simultaneous)
Min. ADC Sample Rate: 30 MHz/ch. (simultaneous)
ADC Resolution: 14 bits
Spurious Free Dynamic Range (SFDR) :Better than 80 dB
Signal-to-Noise Ratio (S/(N+D)) : > 67 dB @105 MHz sampling rate
Crosstalk between channels: > 78 dB
ANALOG OUTPUTS
No. of Analog Output Channels: 2
Analog Connector Type: SMA Coaxial
Full Scale Tx Output : ±1Vpp (50 Ohm source impedance)
Max DAC conversion rate : 210 MHz/ch (simultaneous)
Min DAC Conversion Rate: 2 MHz/ch (simultaneous)
DAC Resolution: 14 bits
Spurious Free Dynamic Range (SFDR) : Better than 70 dB (20 MHz output at 150 MHz conversion rate)
Better than 60 dB (150 MHz output at 210 MHz conversion rate)
Crosstalk between channels : > 78 dB
COMMON TO TX & RX
Sampling/Conversion: Rising edge of sample clock
External trigger: Sampling/Conversion occurs following rising or falling edge of external trigger
(programmable). Trigger must remain high for at least one clock cycle.
User FPGA Type: Standard: Xilinx XC4V SX35FFG668-10
Onboard Storage 64 Mbytes of SDRAM
Mechanical PCI Mezzanine Card (PMC) compatible with IEEE P1386.1
User Programmable I/O on Pn4 connector with LVDS support
GENERAL
PCI bus Interface: PCI 2.2 compliant (64-bit 66MHz), Master/Target Burst Mode (DMA) capable,
with DMA Chaining (Scatter-Gather).
Environmental:
Operating Temp: 0 - +50ºC (at entry point of forced air)
Storage Temp: -40 - +85ºC
Humidity: 90% non-condensing
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