原创 CPLD应用：用Verilog对正交编码器进行解码

CPLD采用的当初采用的是ALTERA EPM240，可以对正交编码器进行4倍频解码，三通道计数。源码部分采用Verilog编写，有兴趣的朋友可以参考参考.

关键部分：
//    ***************************************************************
//
//    AB_DECODER.v        Decoder for phase A and B encoder
//   
//    V1.00    2007-12-04
//
//    Design by lbxxx in shanghai, all right reserved
//
//    ***************************************************************

module AB_DECODER
(
    DI_SYSCLK,
    DI_PHASE_A,
    DI_PHASE_B,   
    DO_PULSE,
    DO_DIRECT
);

//    input
//
input DI_SYSCLK;
input DI_PHASE_A;
input DI_PHASE_B;

//    output
//
output DO_PULSE;
output DO_DIRECT;

//    register
//
reg DO_PULSE;
reg PULSE_DOUBLE;
reg PULSE_DOUBLE_LAST;
reg DIRECT;
reg DIRECT_PATCH;


//    decode direct from phase A and B
//
always @(posedge DI_PHASE_A) DIRECT = DI_PHASE_B;
always @(posedge DI_PHASE_B) DIRECT_PATCH = ~(DIRECT ^ DI_PHASE_A);
assign DO_DIRECT = DIRECT | DIRECT_PATCH;

//    decode pulse from phase A and B
//
always PULSE_DOUBLE = DI_PHASE_A ^ DI_PHASE_B;

always @(posedge DI_SYSCLK) begin

    if(PULSE_DOUBLE != PULSE_DOUBLE_LAST) begin
        DO_PULSE = 1'b1;
        PULSE_DOUBLE_LAST = PULSE_DOUBLE;
    end
    else begin
        DO_PULSE = 1'b0;
    end
   
end

endmodule

Verilog对正交编码器进行解码：
https://static.assets-stash.eet-china.com/album/old-resources/2008/12/1/38020f79-abb7-4c82-83bd-1792f9307817.rar