原创 我的第一个fpga实验程序(verilog hdl语言)

搞了几天了,终于完成了第一个FPGA的程序,速度其实也很慢了,虽然上学期就买了2C5的板,但是接着的期末考拖延了很长时间,没办法了.一步步来吧!

流水灯程序(实现7个流水灯的循环流动,类似于单片机的流水灯)

实验程序如下:

module led_8( clk, led );
input clk;
output [7:0] led;
  reg [7:0] led;
  reg [25:0] buffer;
  always @ (posedge clk)
begin
buffer = buffer +1;
if ( buffer == 26'b11111111111111111111111111)
begin
led=led<<1;
if ( led==8'b00000000 )
led=8'b11111111;
end
end
endmodule

2C5板和管脚分配如下:

#Setup.tcl
# Setup pin setting for EP2C8 main board
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_23 -to clk                           
#seg7led
set_location_assignment PIN_103 -to led\[0\]           
set_location_assignment PIN_101 -to led\[1\]           
set_location_assignment PIN_97 -to led\[2\]           
set_location_assignment PIN_95 -to led\[3\]           
set_location_assignment PIN_92 -to led\[4\]           
set_location_assignment PIN_89 -to led\[5\]           
set_location_assignment PIN_105 -to led\[6\]
set_location_assignment PIN_107 -to led\[7\]

仿真波形图如下(时间上我缩短到2的3次方的延时,方便观看波形变化):