原创 等精度数字频率计

最近在做课程设计,题目是等精度的数字频率计,我们队用FPGA和51单片机结合的1602液晶显示的方法,终于实现了,等精度就是等精度,误差比纯单片机实现的频率计好太多了,由于实验室的信号源只有3MHZ的产生信号,我们暂时只能测试了3M左右,精度达到千分之一,按原理来看应该至少可以测到<50MHZ的.现在先将FPGA部分的程序贴出来.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pinlvji is

 port(
   bclk : in std_logic;
   tclk : in std_logic;
   clr  : in std_logic;
   cl   : in std_logic;
   spul : in std_logic;
   start: out std_logic;
   eend : out std_logic;
   sel  : in std_logic_vector(2 downto 0);
   data : out std_logic_vector(7 downto 0));
 end pinlvji;
 
architecture behav of pinlvji is

 signal bzq,tsq : std_logic_vector(31 downto 0);
 signal ena,pul : std_logic;
 signal ma,clk1,clk2,clk3 :std_logic;
 signal q1,q2,q3,bena :std_logic;
 signal ss : std_logic_vector(1 downto 0);

   begin
 start <= ena;
 data  <=bzq(7 downto 0)  when sel="000"  else
    bzq(15 downto 8)  when sel="001"  else
    bzq(23 downto 16)  when sel="010"  else
    bzq(31 downto 24)  when sel="011"  else
    tsq(7 downto 0)    when sel="100"  else
    tsq(15 downto 8)   when sel="101"  else
    tsq(23 downto 16)  when sel="110"  else
    tsq(31 downto 24)  when sel="111"  else
    tsq(31 downto 24);
  
 bzh : process(bclk,clr)
   begin
    if clr='1' then bzq<=(others=>'0');
    elsif bclk'event and bclk='1'  then
     if bena ='1' then bzq<=bzq+1;
     end if;
    end if;
   end process;
 
 tf : process(tclk,clr,ena)
   begin
    if clr='1' then tsq<=(others=>'0');
    elsif tclk'event and tclk='1'  then
     if ena ='1' then tsq<=tsq+1;
     end if;
    end if;
   end process;
   
 process(tclk,clr)
  begin
   if clr='1' then ena<='0';
   elsif tclk'event and tclk ='1' then ena<=cl;
   end if;
  end process;
  
 ma<=(tclk and cl) or not(tclk or cl);
 clk1<= not ma; clk2<=ma and q1; clk3<= not clk2; ss<= q2& q3;
 
 dd1 : process(clk1,clr)
  begin
   if clr='1' then q1<='0';
   elsif clk1'event and clk1='1' then q1<='1';
   end if;
  end process;
 dd2 : process(clk2,clr)
     begin
   if clr='1' then q2<='0';
   elsif clk2'event and clk2='1' then q2<='1';
   end if;
  end process;
 
 dd3 : process(clk3,clr)
     begin
   if clr='1' then q3<='0';
   elsif clk3'event and clk3='1' then q3<='1';
   end if;
  end process;
  
 pul  <='1'  when ss="10"  else
     '0';
 eend <='1'  when ss="11" else
     '0';
 bena <=ena  when spul='1' else
     pul  when spul='0' else
     pul;
  
end behav;