原创 VHDL

测试代码

LIBRARY ieee;<?xml:namespace prefix = o />

USE ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

ENTITY test_hdl IS

    PORT

    (

       clk      : IN STD_LOGIC;     

       data_in  : IN STD_LOGIC_VECTOR (7 downto 0);

       data_out : out STD_LOGIC_VECTOR (31 downto 0)

    );

END test_hdl;

ARCHITECTURE ONE OF test_hdl IS

signal data_in_buf1 : std_logic_vector(7 downto 0);

signal data_in_buf2 : std_logic_vector(31 downto 0);

begin

process(clk)

begin

if clk'event and clk = '1' then

    data_in_buf1 <= data_in;

end if;

end process;

process(clk)

begin

if clk'event and clk = '1' then

    data_in_buf2 <= data_in_buf1 + data_in_buf2;

end if;

end process;

process(clk)

begin

if clk'event and clk = '1' then

    data_out <= data_in_buf2;

end if;

end process;

end;