library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity duoxing is
generic(ACCWidth : Integer := 16); --相位累加器的长度2^N (2^ACCWidth)
port (
CLK: in std_logic; --系统时钟 FClk
-- STEP: in std_logic_vector(ACCWidth-1 downto 0); --步进,即相位累加器的累加增量,控制输出频率 2^M 频率控制字
CHOICE: in std_logic_vector(1 downto 0); --波形选择信号 "00":正弦; "01":三角波; "10":方波; "11":不输出(恒为低电平)
Key : in std_logic;
DAOUT : out std_logic_vector(7 downto 0) --8位DA输出模拟信号,直通方式,如需时钟控制则要修改
);
end;
architecture dacc of duoxing is
signal ACC:std_logic_vector(ACCWidth-1 downto 0):=(others =>'0');
signal KEYADD:std_logic_vector(ACCWidth-1 downto 0):="0000000011111111";
begin
process(CLK)--,STEP)
begin
if(CLK'event and CLK='1') then
ACC<=ACC+KEYADD;
end if;
end process;
process(key)
begin
if(key' event and key='1') then
KEY<=KEYADD+1;
end if;
end process;
process(CHOICE,ACC)
begin
case CHOICE is
when "00"=> --正弦
case ACC(ACCWidth-1 downto ACCWidth-8) is
when "00000000" => DAOUT <= "10000000";
when "00000001" => DAOUT <= "10000011";
when "00000010" => DAOUT <= "10000110";
when "00000011" => DAOUT <= "10001001";
when "00000100" => DAOUT <= "10001101";
when "00000101" => DAOUT <= "10010000";
省略
when "11111110" => DAOUT <= "01111010";
when "11111111" => DAOUT <= "01111101";
when others => DAOUT <= (others =>'0');
end case;
when "01"=> --三角波
case ACC(ACCWidth-1) is
when '0' => DAOUT <= ACC(ACCWidth-2 downto ACCWidth-9); --模二加,左移一位
when '1' => DAOUT <= ("11111111" - ( ACC(ACCWidth-2 downto ACCWidth-9) ));
when others => DAOUT <= (others =>'0');
end case;
when "10"=> --方波
case ACC(ACCWidth-1) is
when '0' => DAOUT <= (others =>'0');
when '1' => DAOUT <= (others =>'1');
when others => DAOUT <= (others =>'0');
end case ;
when "11" => DAOUT <= ACC(ACCWidth-1 downto ACCWidth-8);
when others => DAOUT <= (others =>'0');
end case;
end process;
end;
出现如下错误:
Error: VHDL error at duoxing.vhd(29): can't write to interface object "Key" of mode IN
Error: VHDL error at duoxing.vhd(29): can't determine definition of operator ""+"" -- found 0 possible definitions
Error: Ignored construct dacc at duoxing.vhd(16) because of previous errors
Info: Found 0 design units, including 0 entities, in source file duoxing.vhd
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