原创 差分控制器设计--Protel99SE自带CUPL语言设计

2007-1-16 00:00 4456 7 7 分类: FPGA/CPLD

Name        PLDDesign9           ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;


/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/


/** Inputs  **/
Pin[1, 11]  = [clk, oe];
Pin[10,20]  = [Gnd,Vcc];
Pin[2..9]   =  [srclk2h, srclk2l, clrh, clrl, rclkh, rclkl, srclk1h, srclk1l];
/** Outputs **/
Pin[12..19] = [g, srclk2, q3..0, srclk1, rclk];


/** Declarations and Intermediate Variables  **/
fld count   = [q3..0];
fld clrx    = [clrh, clrl];
fld rclkx   = [rclkh, rclkl];
fld srclk1x = [srclk1h, srclk1l];
fld srclk2x = [srclk2h, srclk2l];


fld clrxx   = [g, srclk1h, srclk1l, srclk2h, srclk2l, clrh, clrl];
fld enxx    = [clrh, clrl, rclkh, rclkl];
fld rclkxx  = [g, rclkh, rclkl, srclk1h, srclk1l, srclk2h, srclk2l];
fld srclkxx = [g, clrh, clrl, rclkh, rclkl, srclk1h, srclk1l, srclk2h, srclk2l];



$define clear 'b'0101001


 


$define row0 'H'0
$define row1 'H'1
$define row2 'H'2
$define row3 'H'3
$define row4 'H'4
$define row5 'H'5
$define row6 'H'6
$define row7 'H'7
$define row8 'H'8
$define row9 'H'9
$define rowa 'H'a
$define rowb 'H'b
$define rowc 'H'c
$define rowd 'H'd
$define rowe 'H'e
$define rowf 'H'f


/** Logic Equations **/
    !g      = enxx: 'b'0101
            # enxx: 'b'0110
            # enxx: 'b'1001
            # enxx: 'b'1010;


    !rclk   = rclkxx: 'b'0011010;


    !srclk1 = srclkxx: 'b'010100110
            # srclkxx: 'b'010100101;


    !srclk2 = srclkxx: 'b'010101001
            # srclkxx: 'b'010100101;


/** State Definitions **/


sequence count{


present row0:
        if clrxx: clear next row0;
        default next row1;


present row1:
        if clrxx: clear next row0;
        default next row2;


present row2:
        if clrxx: clear next row0;
        default next row3;


present row3:
        if clrxx: clear next row0;
        default next row4;


present row4:
        if clrxx: clear next row0;
        default next row5;


present row5:
        if clrxx: clear next row0;
        default next row6;


present row6:
        if clrxx: clear next row0;
        default next row7;


present row7:
        if clrxx: clear next row0;
        default next row8;


present row8:
        if clrxx: clear next row0;
        default next row9;


present row9:
        if clrxx: clear next row0;
        default next rowa;


present rowa:
        if clrxx: clear next row0;
        default next rowb;


present rowb:
        if clrxx: clear next row0;
        default next rowc;


present rowc:
        if clrxx: clear next row0;
        default next rowd;


present rowd:
        if clrxx: clear next row0;
        default next rowe;


present rowe:
        if clrxx: clear next row0;
        default next rowf;


present rowf:
        next row0;


}

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