A PCI diode-enabled pin only affects signal voltage about 0.7 V above VCCIO level. Higher voltage levels are clipped, effectively reducing voltage level at pin to about VCCIO + 0.7-V level. 0.7 V is an approximation of the on-chip diode turn-on voltage.
Use when the voltage overshoot seen at the FPGA pin exceeds acceptable maximum level. FPGAs in the Cyclone family have maximum DC input and maximum overshoot (AC) voltage specifications.
Use when interfacing a Cyclone II FPGA or a Cyclone FPGA with a 5.0-V LVTTL device to clamp voltage at the FPGA pin to an acceptable maximum level.
For all cases of usage, determine if series resistor is needed to reduce DC current to acceptable limit through the on-chip diode.
How to Use
In the Assignment Editor, set the PCI I/O assignment to ON to enable the on-chip clamp diode for the pin.
Feature Availability
All banks of user I/O pins for Cyclone III FPGAs.
Only with side bank user I/O pins for Cyclone II and Cyclone FPGAs.
Feature Limitations
Not supported in dedicated input clock and configuration pins.
There is a maximum of 10-mA DC current through the on-chip clamp diode for Cyclone III FPGAs and 25- mA for Cyclone II and Cyclone FPGAs.
Not available in dual-purpose configuration pins that are used during configuration for FPGAs in the Cyclone III family.
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