原创 cyclone 系列IO口问题--开漏输出与上拉电阻设置

2008-12-26 17:14 4390 0 分类: FPGA/CPLD
转自:http://www.altera.com/support/devices/io/features/io-features.html

可以设置这两个项。
引脚的上拉电阻可以和三态输出,开漏输出结合使用。
可是三态输入输出(双向引脚)就不知怎么用了

Programmable Open-Drain Output



When to Use




  • An open-drain output provides a high-impedance state on output when logic-to-pin is high. If logic-to-pin is low, output is low.


  • More than one open-drain output can be attached to a single wire.
    This type of connection is analogous to a logical OR function and is
    commonly termed as an active-low wired-OR circuit. If at least one of
    the outputs is in the logic 0 state (active), it sinks the current and
    brings the line to low voltage.


  • Use when connecting multiple devices to a bus. For example,
    system-level control signals that can be asserted by any device or as
    an interrupt.



How to Use




  • There are two ways to enable the open-drain output assignment:



    • OPNDRN primitive—Design the tri-state buffer with an OPNDRN
      primitive. The input to the primitive is equivalent to the Output
      Enable (OE) signal when using a TRI primitive.


    • Auto Open-Drain Pins option—This is a global setting that directs
      the compiler to automatically convert a tri-state buffer (usually with
      TRI primitive) with a fixed low data input into the equivalent
      open-drain buffer throughout the design. This option is enabled by
      default.



  • You can design open-drain output without enabling the option
    assignment. In that case, you are not utilizing the open-drain output
    feature in the I/O buffer. Using the open-drain output feature in the
    I/O buffer provides you the best propagation delay, tpd from OE to
    output.


  • Support solution rd06252007_878 shows an example of how you can implement the open-drain output using standard VHDL or Verilog HDL statements.



Feature Availability




  • All user I/Os are used as output or bidirectional pins.


  • Can be used along with programmable pull-up resistor.



Feature Limitation




  • Not available in dedicated configuration pins.

Programmable Pull-up Resistor

When to Use



  • Use when there is a need to pull a pin signal level to VCCIO when it is tri-stated.
  • Use to replace a weak external pull-up resistor. The pull-up
    resistance varies with process, voltage, and temperature conditions.
  • Use external components if you require precision values.
  • Use in combination with open-drain output option.


How to Use



  • In the Assignment Editor, set the weak pull-up assignment to ON to enable the on-chip pull-up resistor for the pin.


Feature Availability




  • All user I/Os.



Feature Limitations



  • Not supported in dedicated configuration pins and dedicated clock input pins.
  • Not available in pins that are using bus hold option.


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