/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* 文件名称: stm32f10x_can.c
* 程序作者: MCD Application Team
* 程序版本: V2.0.2
* 编制日期: 07/11/2008
* 功能描述: 这个文件提供了所有CAN的固件函数.
********************************************************************************
* 目前的固件的目的是为客户提供关于他们的产品的编码信息以便于节省他们时间。
* 结果, 意法半导体将不会为此承担任何直接,间接或相应的损害赔偿方面的任何索赔要求,
* 例如固件或使用所作的客户编码中他涉嫌包含与他们的相关产品的信息。
*******************************************************************************/
/* 包涵的文件 ------------------------------------------------------------------*/
#include "stm32f10x_can.h"
#include "stm32f10x_rcc.h"
/* 自用类型 -----------------------------------------------------------*/
/* 自用定义 ------------------------------------------------------------*/
/* CAN Master Control Register bits [CAN主控寄存器位]*/
#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request [初始化请求]*/
#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request [睡眠模式请求]*/
#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority [发送FIFO优先级]*/
#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode [接收FIFO锁定模式]*/
#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission [非自动重发]*/
#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode [自动唤醒模式]*/
#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management [自动总线关断管理]*/
#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication [定时器触发通讯]*/
/* CAN Master Status Register bits [CAN主控模式状态寄存器位]*/
#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge [初始化确认]*/
#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt [唤醒中断]*/
#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt [睡眠确认中断]*/
/* CAN Transmit Status Register bits [CAN发送状态寄存器位]*/
#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 [信箱0完成请求]*/
#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 [信箱0发送OK]*/
#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 [信箱0请求失败]*/
#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 [信箱1完成请求]*/
#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 [信箱1发送OK]*/
#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 [信箱1请求失败]*/
#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 [信箱2完成请求]*/
#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 [信箱1发送OK]*/
#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 [信箱2请求失败]*/
#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty [发送信箱0空]*/
#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty [发送信箱1空]*/
#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty [发送信箱2空]*/
/* CAN Receive FIFO 0 Register bits [CAN接收FIFO 0寄存器位]*/
#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full [FIFO 0满]*/
#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun [FIFO 0溢出]*/
#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox [释放FIFO 0输出信箱]*/
/* CAN Receive FIFO 1 Register bits [CAN接收FIFO 1寄存器位]*/
#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full [FIFO 1满]*/
#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun [FIFO 1溢出]*/
#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox [释放FIFO 1输出信箱]*/
/* CAN Error Status Register bits [CAN错误状态寄存器位]*/
#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag [错误警告标志]*/
#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag [错误被动标志]*/
#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag [总线关断标志]*/
/* CAN Mailbox Transmit Request [CAN信箱发送请求]*/
#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request [发送信箱请求]*/
/* CAN Filter Master Register bits [CAN滤波器主寄存器位]*/
#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode [滤波器初始化模式]*/
/* 自用宏 -------------------------------------------------------------*/
/* 自用变量 ---------------------------------------------------------*/
/* 自用函数原型 -----------------------------------------------*/
static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
}
用户1182575 2012-5-20 12:01