原创 FPGA驱动74HC595程序，见笑了，处女作。

library ieee;
use ieee.std_logic_1164.all;

entity hc595 is
 port(clk: in std_logic;
   shift_clk: out std_logic;   //移位时钟 
   storage_clk: out std_logic; //锁存时钟
   ds: out std_logic           //移位输出数据
 );
end hc595;

architecture behavior of hc595 is
 type state_type is(shift_output, wait_bit_tranfer, storage_output, stop); //4个状态
 signal state: state_type;
 signal clk_10M: std_logic; //50M全局时钟分频得到
 signal write_byte: std_logic_vector(7 downto 0) := "10101010";//待输出的数据
 signal output_bit_count: integer range 0 to 8;//输出位计数，需要输出八次
 signal shift_clk_output_enable, storage_clk_output_enable: std_logic := '0';//进程间通信信号，由状态机驱动
begin
div_clk:  //分频进程
 process(clk)
  variable count: integer range 0 to 2;
 begin
  if(rising_edge(clk)) then
   if(count = 2) then
    clk_10M <= not clk_10M;
    count := 0;
   else
    count := count+1;
   end if;
  end if;
 end process;
 
shift_clk_output_en: //移位时钟驱动进程
 process(shift_clk_output_enable,clk_10M,clk)
 variable count_clk: integer range 0 to 1;
 begin
  if(shift_clk_output_enable = '1') then
   if(rising_edge(clk)) then
    if(count_clk = 1) then
     shift_clk <= clk_10M;
    else
     count_clk := count_clk+1;
    end if;
   end if;
  end if;
 end process;
 
storage_clk_output_en://锁存时钟驱动进程
 process(storage_clk_output_enable,clk_10M,clk)
 variable count_clk: integer range 0 to 2;
 begin
  if(storage_clk_output_enable = '1') then
   if(rising_edge(clk)) then
    if(count_clk = 2) then
     storage_clk <= clk_10M;
    else
     count_clk := count_clk+1;
    end if;
   end if;
  end if;
 end process;
 
shift_bit_output://数据移位输出
 process(clk_10M)
 begin
  if(rising_edge(clk_10M)) then
   ds <= write_byte(output_bit_count);
   output_bit_count <= output_bit_count + 1;
  end if;
 end process;
 
state_transfer://状态机转换
 process(clk, state, output_bit_count)
 begin
  if(rising_edge(clk)) then
   case state is
    when shift_output =>
     shift_clk_output_enable <= '1';
     state <= wait_bit_tranfer;
     
    when wait_bit_tranfer =>
     if(output_bit_count = 8) then
      state <= storage_output;
     else
      state <= shift_output;
     end if;
    when storage_output =>
     storage_clk_output_enable <= '1';
     state <= stop;
    when stop =>
     shift_clk_output_enable <= '0';
     state <= stop;
   end case;
  end if;
 end process;
end behavior;