原创 FSM 状态机输出方法

2010-1-3 16:47 3216 5 5 分类: FPGA/CPLD

The outputs can be generated in one of several ways :


As a combinatorial function of the present state vector and the inputs

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As a synchronous function of the present state vector and the inputs.


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As a synchronous function of the next state vector and the inputs


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