原创 xilinx spartan-3A ( XC3S400A) UART

+------------------------------------------------------------------------------------+
| Module    | Slices | Slice Reg | LUTs  | LUTRAM | Full Hierarchical Name           |
+-----------+--------+-----------+-------+--------+----------------------------------+
| +uart_i   | 5/48   | 6/50      | 5/73  | 0/36   | arm_top/uart_i                   |
| ++receive | 0/24   | 0/29      | 0/38  | 0/27   | arm_top/uart_i/receive           |
| +++buf    | 9/9    | 5/5       | 16/16 | 8/8    | arm_top/uart_i/receive/buf       |
| +++kcuart | 15/15  | 24/24     | 22/22 | 19/19  | arm_top/uart_i/receive/kcuart    |
| ++transmit| 0/19   | 0/15      | 0/30  | 0/9    | arm_top/uart_i/transmit          |
| +++buf    | 9/9    | 5/5       | 16/16 | 8/8    | arm_top/uart_i/transmit/buf      |
| +++kcuart | 10/10  | 10/10     | 14/14 | 1/1    | arm_top/uart_i/transmit/kcuart   |
+------------------------------------------------------------------------------------+

----------------------------------------------------------------------------------
-- UART 
----------------------------------------------------------------------------------
--
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
-- Each contains an embedded 16-byte FIFO buffer.
--
-- Company:
-- Engineer:
--
-- Create Date:    22:11:18 12/13/2009
-- Design Name:
-- Module Name:    uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity uart is
 generic (
  clk_freq : integer range 0 to 100_000_000 := 16_000_000;
  baud_rate : integer range 0 to 6_000_000 := 115200
 );
 
 PORT (
  clk : in std_logic;
  rst : in std_logic;
  
  uart_tx_pin : out std_logic;
  uart_rx_pin : in std_logic;
  
  uart_read_buffer  : in std_logic;
  uart_write_buffer : in std_logic;
  
  uart_tx_data : in std_logic_vector(7 downto 0);
  uart_rx_data : out std_logic_vector(7 downto 0);
  
  uart_status : out std_logic_vector(7 downto 0)
 );

end uart;

architecture Behavioral of uart is

COMPONENT uart_tx
PORT(
 clk : IN std_logic;         
 en_16_x_baud : IN std_logic;
 serial_out : OUT std_logic;
 data_in : IN std_logic_vector(7 downto 0);

 write_buffer : IN std_logic;
 reset_buffer : IN std_logic;
 
 buffer_full : OUT std_logic;
 buffer_half_full : OUT std_logic
 );
END COMPONENT;

COMPONENT uart_rx
PORT(
 clk : IN std_logic;         
 en_16_x_baud : IN std_logic;
 serial_in : IN std_logic;
 data_out : OUT std_logic_vector(7 downto 0);
 
 read_buffer : IN std_logic;
 reset_buffer : IN std_logic;
 
 buffer_data_present : OUT std_logic;
 buffer_full : OUT std_logic;
 buffer_half_full : OUT std_logic
 );
END COMPONENT;

constant baud_count_limit : positive := clk_freq/16/baud_rate - 1;

signal       baud_count : integer range 0 to 31 :=0;
signal     en_16_x_baud : std_logic;

signal          tx_full : std_logic;
signal     tx_half_full : std_logic;
signal  rx_data_present : std_logic;
signal          rx_full : std_logic;
signal     rx_half_full : std_logic;

begin

 uart_status <= '0' & rx_data_present & rx_half_full & rx_full & "00" & tx_half_full & tx_full;
  
  transmit: uart_tx
  port map (              data_in => uart_tx_data,
                     write_buffer => uart_write_buffer,
                     reset_buffer => rst,
                     en_16_x_baud => en_16_x_baud,
                       serial_out => uart_tx_pin,
                      buffer_full => tx_full,
                 buffer_half_full => tx_half_full,
                              clk => clk );

  receive: uart_rx
  port map (            serial_in => uart_rx_pin,
                         data_out => uart_rx_data,
                      read_buffer => uart_read_buffer,
                     reset_buffer => rst,
                     en_16_x_baud => en_16_x_baud,
              buffer_data_present => rx_data_present,
                      buffer_full => rx_full,
                 buffer_half_full => rx_half_full,
                              clk => clk ); 
 
  --
  -- Set baud rate to 9600 for the UART communications
  -- Requires en_16_x_baud to be 153600Hz which is a single cycle pulse every 326 cycles at 50MHz
  -- 50_000_000 / 9600 / 16 = 325.5 = 326
 --
  baud_timer: process(clk)
  begin
    if clk'event and clk='1' then
      if baud_count=baud_count_limit then
         baud_count <= 0;
         en_16_x_baud <= '1';
       else
         baud_count <= baud_count + 1;
         en_16_x_baud <= '0';
      end if;
    end if;
  end process baud_timer;

end Behavioral;