原创 microblaze SDRAM

 2010-12-22 08:55  2476 10 10 分类: FPGA/CPLD

BEGIN mpmc
PARAMETER INSTANCE = mpmc_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_MEM_PARTNO = MT48LC32M16A2-75
PARAMETER C_MEM_TYPE = SDRAM
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_MPMC_BASEADDR = 0x80000000
PARAMETER C_MPMC_HIGHADDR = 0x83FFFFFF
PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_XCL0_B_IN_USE = 1
PARAMETER C_USE_STATIC_PHY = 1
BUS_INTERFACE XCL0 = microblaze_0_IXCL
BUS_INTERFACE XCL0_B = microblaze_0_DXCL
BUS_INTERFACE MPMC_CTRL = mb_plb
PORT MPMC_Clk0 = clk_100_0000MHz
PORT MPMC_DCM_PSINCDEC = Static_Phy_DCM_PSINCDEC
PORT MPMC_DCM_PSEN = Static_Phy_DCM_PSEN
PORT MPMC_DCM_PSDONE = Static_Phy_DCM_PSDONE
PORT MPMC_Clk_Mem = MPMC_Clk_Mem
PORT SDRAM_DM = mpmc_0_SDRAM_DM
PORT SDRAM_DQ = mpmc_0_SDRAM_DQ
PORT SDRAM_Addr = mpmc_0_SDRAM_Addr
PORT SDRAM_BankAddr = mpmc_0_SDRAM_BankAddr
PORT SDRAM_WE_n = mpmc_0_SDRAM_WE_n
PORT SDRAM_CAS_n = mpmc_0_SDRAM_CAS_n
PORT SDRAM_RAS_n = mpmc_0_SDRAM_RAS_n
PORT SDRAM_CS_n = mpmc_0_SDRAM_CS_n
PORT SDRAM_CE = mpmc_0_SDRAM_CE
PORT SDRAM_Clk = mpmc_0_SDRAM_Clk
PORT MPMC_Rst = sys_periph_reset

END

Also, your mpmc static PHY needs a second clock, phase shifted from its other clock, so you need to configure your clock generator to produce this phase shigfted clock and connect it to mpmc. Again see my example MHS file. It is in the mpmc section called MPMC_Clk_Mem.

PORT fpga_0_SDRAM_Clk_pin = fpga_0_SDRAM_Clk, DIR = O, VEC = [0:0], SIGIS = CLK
PORT fpga_0_SDRAM_CE_pin = fpga_0_SDRAM_CE, DIR = O, VEC = [0:0]
PORT fpga_0_SDRAM_CS_n_pin = fpga_0_SDRAM_CS_n, DIR = O, VEC = [0:0]
PORT fpga_0_SDRAM_RAS_n_pin = fpga_0_SDRAM_RAS_n, DIR = O
PORT fpga_0_SDRAM_CAS_n_pin = fpga_0_SDRAM_CAS_n, DIR = O
PORT fpga_0_SDRAM_WE_n_pin = fpga_0_SDRAM_WE_n, DIR = O
PORT fpga_0_SDRAM_BankAddr_pin = fpga_0_SDRAM_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_SDRAM_Addr_pin = fpga_0_SDRAM_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_SDRAM_DQ_pin = fpga_0_SDRAM_DQ, DIR = IO, VEC = [7:0]
PORT fpga_0_SDRAM_DM_pin = fpga_0_SDRAM_DM, DIR = O, VEC = [0:0]

BEGIN mpmc
PARAMETER INSTANCE = SDRAM
PARAMETER HW_VER = 5.00.a
PARAMETER C_MEM_PARTNO = MT48LC32M8A2-75
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x01FFFFFF
PARAMETER C_MEM_TYPE = SDRAM
PARAMETER C_MEM_DATA_WIDTH = 8
PARAMETER C_USE_STATIC_PHY = 1
PARAMETER C_MPMC_CTRL_HIGHADDR = 0x00000000
PARAMETER C_MPMC_CTRL_BASEADDR = 0xFFFFFFFF
BUS_INTERFACE SPLB0 = plb
PORT SDRAM_Clk = fpga_0_SDRAM_Clk
PORT SDRAM_CE = fpga_0_SDRAM_CE
PORT SDRAM_CS_n = fpga_0_SDRAM_CS_n
PORT SDRAM_RAS_n = fpga_0_SDRAM_RAS_n
PORT SDRAM_CAS_n = fpga_0_SDRAM_CAS_n
PORT SDRAM_WE_n = fpga_0_SDRAM_WE_n
PORT SDRAM_BankAddr = fpga_0_SDRAM_BankAddr
PORT SDRAM_Addr = fpga_0_SDRAM_Addr
PORT SDRAM_DQ = fpga_0_SDRAM_DQ
PORT SDRAM_DM = fpga_0_SDRAM_DM
END