原创 FPGA课堂实验一：流水灯

           最近我们学习显示驱动技术，第一次实验，流水灯。开始本来想用移位来实现的，后来在状态转移那个部分没有仿真出来，就直接用最简单的方法做了。

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Engineer  : chick_kid
// Create Date : 2009.05.12
// Design Name :
// Module Name : led
// Project Name : led
// Target Device: Cyclone EP1C3T144C8
// Tool versions: Quartus II 9.1
// Description : 流水灯

////////////////////////////////////////////////////////////////////////////////
module led(
            clk,rst_n,
            led
           );
  
input clk;                  //输入时钟50Mhz
input rst_n;               //复位

output[7:0] led;          //输出8个led灯

reg[7:0] led_reg;        //输出8个led灯寄存器

reg[24:0] ct1;             //定时计数器，20ns*25000000

always @(posedge clk or negedge rst_n)
begin
     if(!rst_n)
        ct1 <= 25'd0;
     else if (ct1 == 25'd24_999_999)  
        ct1 <= 25'd0;
     else
        ct1 <= ct1 + 1'b1;
end

wire clk_div = (ct1 == 25'd24_999_999);   //定时满足条件，给一个高电平

reg[3:0] state;                 //状态寄存器
always @(posedge clk_div or negedge rst_n)
begin
     if(!rst_n)
        state <= 4'd0;
     else if (state == 4'd13)   
        state <= 4'd0;
     else 
        state <= state + 4'd1;
end

always @(posedge clk or negedge rst_n)           
begin
     if(!rst_n)
        led_reg <= 8'b0000_0000;
     case (state)     
       4'd0  : led_reg <= 8'b0000_0001;  
       4'd1  : led_reg <= 8'b0000_0010;  
       4'd2  : led_reg <= 8'b0000_0100;  
       4'd3  : led_reg <= 8'b0000_1000; 
       4'd4  : led_reg <= 8'b0001_0000;  
       4'd5  : led_reg <= 8'b0010_0000;  
       4'd6  : led_reg <= 8'b0100_0000;  
       4'd7  : led_reg <= 8'b1000_0000;  
       4'd8  : led_reg <= 8'b0100_0000;  
       4'd9  : led_reg <= 8'b0010_0000;  
       4'd10 : led_reg <= 8'b0001_0000;  
       4'd11 : led_reg <= 8'b0000_1000;  
       4'd12 : led_reg <= 8'b0000_0100;  
       4'd13 : led_reg <= 8'b0000_0010;  
     default : led_reg <= 8'b0000_0000;
     endcase
end

assign led = led_reg;
endmodule

但是编译有2个warning

Warning: Circuit may not operate. Detected 13 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.

Warning: Found 32 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
 Info: Detected ripple clock "ct1[1]" as buffer
 Info: Detected ripple clock "ct1[3]" as buffer
 Info: Detected ripple clock "ct1[2]" as buffer
 Info: Detected ripple clock "ct1[5]" as buffer
 Info: Detected ripple clock "ct1[6]" as buffer
 Info: Detected ripple clock "ct1[7]" as buffer
 Info: Detected ripple clock "ct1[4]" as buffer
 Info: Detected ripple clock "ct1[9]" as buffer
 Info: Detected ripple clock "ct1[11]" as buffer
 Info: Detected ripple clock "ct1[10]" as buffer
 Info: Detected ripple clock "ct1[8]" as buffer
 Info: Detected ripple clock "ct1[12]" as buffer
 Info: Detected ripple clock "ct1[14]" as buffer
 Info: Detected ripple clock "ct1[13]" as buffer
 Info: Detected ripple clock "ct1[15]" as buffer
 Info: Detected ripple clock "ct1[20]" as buffer
 Info: Detected ripple clock "ct1[23]" as buffer
 Info: Detected ripple clock "ct1[22]" as buffer
 Info: Detected ripple clock "ct1[21]" as buffer
 Info: Detected ripple clock "ct1[17]" as buffer
 Info: Detected ripple clock "ct1[19]" as buffer
 Info: Detected ripple clock "ct1[18]" as buffer
 Info: Detected ripple clock "ct1[16]" as buffer
 Info: Detected gated clock "Equal0~0" as buffer
 Info: Detected gated clock "Equal0~1" as buffer
 Info: Detected gated clock "Equal0~2" as buffer
 Info: Detected gated clock "Equal0~3" as buffer
 Info: Detected gated clock "Equal0~6" as buffer
 Info: Detected gated clock "Equal0~5" as buffer
 Info: Detected ripple clock "ct1[24]" as buffer
 Info: Detected gated clock "Equal0" as buffer
 Info: Detected ripple clock "ct1[0]" as buffer

2个都是有关时序的问题，之前也看过handbook上面的关于timing的建立时间也保持时间，但是没有看懂，也没有彻底的理解，，这个问题留着吧，有时间我一定好好琢磨下。