原创 心得:阴级数码管的使用

2010-3-9 19:38 1886 7 7 分类: FPGA/CPLD

      


   从这张图可以看出数码管的的阴极管是低电平有效的(即当0时才能触发阴极管亮),因此真正能让灯显示我要的数字的话,就一定要搞懂这点,举例而言:数字5的话,abcdefg的数字是0100100,而gfedcba的话就是0010010了,其他的具体的gfedcba码如下:


      注意配置的时候,bit7-bit0是gfedcba


           s0 = 7'b1000000,           


           s1 = 7'b1111001, 
           s2 = 7'b0100100, 
           s3 = 7'b0110000, 
           s4 = 7'b0011001, 
           s5 = 7'b0010010, 
           s6 = 7'b0000010, 
           s7 = 7'b1111000, 
           s8 = 7'b0000000, 
           s9 = 7'b0011000,
           sa = 7'b0001000,
           sb = 7'b0000011,  
           sc = 7'b1000110, 
           sd = 7'b0100001,  
           se = 7'b0000110,  
           sf = 7'b0001110;


 


//本实验的功能为:每过一秒,从0循环演变到F
module hex_1f(clk,reset,led);
 input clk;
 input reset;


 output [6:0] led;


 reg [6:0] led;
 reg [7:0] state="8"'d0;
 
 parameter  s0 = 7'b1000000,
      s1 = 7'b1111001,
      s2 = 7'b0100100,
      s3 = 7'b0110000,
      s4 = 7'b0011001,
      s5 = 7'b0010010,
      s6 = 7'b0000010,
      s7 = 7'b1111000,
      s8 = 7'b0000000,
      s9 = 7'b0011000,
      sa = 7'b0001000,
      sb = 7'b0000011, 
      sc = 7'b1000110,
      sd = 7'b0100001, 
      se = 7'b0000110, 
      sf = 7'b0001110;
        
always @(posedge clk)
begin
 if(!reset)
  begin
   led = 7'd0;
   state=8'd0;
  end


 else if(state==8'd15)
   state<=8'd0;
 else
   begin
  case(state)
   8'd0: led =s0; 
   8'd1: led =s1;
   8'd2: led =s2;
   8'd3: led =s3;
   8'd4: led =s4;
   8'd5: led =s5;
   8'd6: led =s6;
   8'd7: led =s7;
   8'd8: led =s8;
   8'd9: led =s9;
   8'd10:led =sa;
   8'd11:led =sb;
   8'd12:led =sc;
   8'd13:led =sd;
   8'd14:led =se;
   8'd15:led =sf;
   default:led=s0;
  endcase
  state=state+1'b1;
    end
end


endmodule

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