原创 串口发送成功

今天走出了FPGA学习过程的第二步，用状态机做了一个串口发送的程序，霍霍，虽然有点sb，但是还是可以运行的，能够在电脑上接收到正确的数据

明天再来做接收的吧

p1:process(clkout)
 begin
  if clkout'event and clkout='1' then
    currentstate <= nextstate;
  end if;
 end process p1;
--***************
--send the data--
--***************
 s1:process(currentstate,data_buffer1)
 variable data_buffer2 : std_logic_vector(7 downto 0);
 begin 
  case currentstate is
   when free =>
    tx_data <='1';
   when loading =>
    tx_data <='1';data_buffer2 :=data_buffer1;
   when send_start =>
    tx_data <='0';
   when send_bit0 =>
    tx_data <=data_buffer2(0);
   when send_bit1 =>
    tx_data <=data_buffer2(1);
   when send_bit2 =>
    tx_data <=data_buffer2(2);
   when send_bit3 =>
    tx_data <=data_buffer2(3);
   when send_bit4 =>
    tx_data <=data_buffer2(4);
   when send_bit5 =>
    tx_data <=data_buffer2(5);
   when send_bit6 =>
    tx_data <=data_buffer2(6);
   when send_bit7 =>
    tx_data <=data_buffer2(7);
   when send_stop =>
    tx_data <='1';
  end case;
 end process s1;
--*********************
--state convert rule
--*********************
 s3:process(currentstate)
 begin
  case currentstate is
   when free   => nextstate <=loading;
   when loading  => nextstate <=send_start;
   when send_start  => nextstate <=send_bit0;
   when send_bit0   => nextstate <=send_bit1;
   when send_bit1   => nextstate <=send_bit2;
   when send_bit2   => nextstate <=send_bit3;
   when send_bit3   => nextstate <=send_bit4;
   when send_bit4   => nextstate <=send_bit5;
   when send_bit5   => nextstate <=send_bit6;
   when send_bit6   => nextstate <=send_bit7;
   when send_bit7  => nextstate <=send_stop;
   when send_stop   => nextstate <=free;
  end case;
 end process s3;
--********************************
--generate the baud rate for usart
--********************************
 process(clkin)
 begin
  if clkin'event and clkin='1'then
   if tmp=2604 then
    outdata<=not outdata;
    tmp<=0;
   else
    tmp<=tmp + 1;
   end if;
  end if;
 end process;