`timescale 1ns/100ps
module scan_led( clk,
rst_n,
din,
seg,
cs);
input clk;
input rst_n;
input [31:0] din;
output reg [6:0] seg;
output reg [7:0] cs;
reg [2:0] count;
always @(posedge clk)
count <= count + 1;
//共阴极数码管，cs低电平有效；
always @(rst_n or count)
if(!rst_n)
cs = 8'b1111_1111;
else
case(count)
3'b000: cs = 8'b1111_1110;
3'b001: cs = 8'b1111_1101;
3'b010: cs = 8'b1111_1011;
3'b011: cs = 8'b1111_0111;
3'b100: cs = 8'b1110_1111;
3'b101: cs = 8'b1101_1111;
3'b110: cs = 8'b1011_1111;
3'b111: cs = 8'b0111_1111;
default:;
endcase
reg [7:0] seg_r;
always @(count or din)
case(count)
3'b000: seg_r = din[3:0];
3'b001: seg_r = din[7:4];
3'b010: seg_r = din[11:8];
3'b011: seg_r = din[15:12];
3'b100: seg_r = din[19:16];
3'b101: seg_r = din[23:20];
3'b110: seg_r = din[27:24];
3'b111: seg_r = din[31:28];
default:;
endcase
//seg[6:0] == {a,b,c,d,e,f,g}
always @(rst_n or seg_r)
if(!rst_n)
seg = 7'b000_0000;
else
case(seg_r)
4'b0000: seg = 7'b111_1110;//0
4'b0001: seg = 7'b011_0000;//1
4'b0010: seg = 7'b110_1101;//2
4'b0011: seg = 7'b111_1001;//3
4'b0100: seg = 7'b011_0011;//4
4'b0101: seg = 7'b101_1011;//5
4'b0110: seg = 7'b101_1111;//6
4'b0111: seg = 7'b111_0000;//7
4'b1000: seg = 7'b111_1111;//8
4'b1001: seg = 7'b111_1011;//9
4'b1010: seg = 7'b111_0111;//A
4'b1011: seg = 7'b001_1111;//b
4'b1100: seg = 7'b100_1110;//C
4'b1101: seg = 7'b011_1101;//d
4'b1110: seg = 7'b100_1111;//E
4'b1111: seg = 7'b100_0111;//F
default: ;
endcase
endmodule
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