原创 验证和建模方法文章汇总

Aldec Events

Aldec Design and Verification Newsletter

Thu Jul 08 2010 09:02:56 GMT+0800 (LONT) 用原型系统确保早期协同仿真验证

Thu Jun 24 2010 16:15:29 GMT+0800 (LONT) How to make virtual prototyping better than
designing with hardware

Thu Jun 24 2010 15:04:17 GMT+0800 (China Standard Time) Virtual debug interface speeds software development

Thu Jun 24 2010 15:00:26 GMT+0800 (China Standard Time) Achieving verification closure with resource and time
constraints

Thu Jun 24 2010 14:58:20 GMT+0800 (China Standard Time) PRODUCT HOW-TO: Verifying your Configurable OCP Interface

Wed Jun 02 2010 18:05:23 GMT-0700 (Pacific Daylight Time) Transitioning from C/C++ to SystemC in high-level design It's far easier to do architecture design in
SystemC than it is to do it in C and C++. If co-designing hardware and software
using high-level design methods, much of your work will be done in an
architecture design phase in SystemC. Here's why.

Wed Jun 02 2010 18:04:34 GMT-0700 (Pacific Daylight Time) A monitor-based approach to verification

Mon May 31 2010 02:07:43 GMT-0700 (Pacific Daylight Time) Taming military/aerospace enterprise system complexity with model-based
requirements planning

Mon May 31 2010 02:06:34 GMT-0700 (Pacific Daylight Time) Code coverage convergence in configurable IP

Mon May 31 2010 02:05:55 GMT-0700 (Pacific Daylight Time) Meeting growing verification demands

Mon May 31 2010 02:05:08 GMT-0700 (Pacific Daylight Time) Using unified modeling methods to reduce embedded
hardware/software development

Mon May 31 2010 02:04:24 GMT-0700 (Pacific Daylight Time) Doing C-code generation better: from graphical code to embedded target

Mon May 31 2010 02:03:14 GMT-0700 (Pacific Daylight Time) Startup rolls automatic assertion synthesis tool

Mon Apr 12 2010 17:23:11 GMT+0800 (China Standard Time) The basics of setting up hardware verification testbenches using OVM
configuration classes

Mon Apr 12 2010 17:22:22 GMT+0800 (China Standard Time) PRODUCT HOW-TO: State machine design is as easy as telling the time

Thu Mar 11 2010 13:34:19 GMT+0800 (China Standard Time) ICE debugging: The end of the battleship game

Mon Mar 01 2010 09:54:16 GMT+0800 (China Standard Time) 浮点模型的定点化到产品级代码的生成

Thu Feb 25 2010 14:06:46 GMT+0800 (China Standard Time) Reducing Costs, Risks, Time to Market with Virtualized
Systems Development

Thu Feb 25 2010 14:01:50 GMT+0800 (China Standard Time) Help — All of my simulations are passing!

Thu Feb 25 2010 14:00:35 GMT+0800 (China Standard Time) Guidelines for complex SoC verification A plan-manage-execute approach to verification

Thu Feb 25 2010 13:51:46 GMT+0800 (China Standard Time) High-level synthesis, verification and language

Sun Feb 07 2010 18:18:17 GMT-0800 (Pacific Standard Time) Layering it on--a new approach to automating system tests

Sun Feb 07 2010 18:17:48 GMT-0800 (Pacific Standard Time) Researchers propose commonsense plan to improve verification process

Sun Feb 07 2010 18:16:59 GMT-0800 (Pacific Standard Time) Managing Complex SoC verification using plan based
verification techniques

Thu Feb 04 2010 17:22:47 GMT-0800 (Pacific Standard Time) Debugging and analysis with SystemVerilog test bench

Thu Feb 04 2010 17:21:31 GMT-0800 (Pacific Standard Time) Can C beat RTL?

Wed Feb 03 2010 18:38:01 GMT-0800 (Pacific Standard Time) Formal verification with constraints — It doesn't have to be
like tightrope walking

Tue Jan 26 2010 21:03:46 GMT-0800 (Pacific Standard Time) Embedded system virtualization for executable specifications
and use case modeling

Sun Jan 24 2010 21:33:35 GMT-0800 (Pacific Standard Time) Applying virtual system integration and test to validate
requirements and verify designs

Sun Jan 24 2010 21:32:48 GMT-0800 (Pacific Standard Time) Early verification cuts design time and cost in
algorithm-intensive systems

Tue Jan 19 2010 21:06:26 GMT-0800 (Pacific Standard Time) Study gives mixed marks to high-level synthesis

Sun Jan 17 2010 21:20:00 GMT-0800 (Pacific Standard Time) Low power LDPC decoder created using high level synthesis

Sun Jan 17 2010 21:17:01 GMT-0800 (Pacific Standard Time) A real solution for mixed signal SoC verification

Fri Jan 08 2010 01:59:35 GMT-0800 (Pacific Standard Time) SOFTWARE TOOLS - PetaLogix Launches First Linux SDK for FPGA-based Embedded
Systems

Fri Jan 08 2010 01:57:34 GMT-0800 (Pacific Standard Time) Firms integrate toolkit for hardware/software
co-simulation

Fri Jan 08 2010 01:49:48 GMT-0800 (Pacific Standard Time) Low power design is here to stay

Tue Jan 05 2010 17:27:20 GMT-0800 (Pacific Standard Time) A unified, scalable SystemVerilog approach to chip and subsystem verification

Tue Jan 05 2010 17:14:56 GMT-0800 (Pacific Standard Time) Using OVM to reuse vital verification knowledge

Mon Dec 28 2009 00:30:22 GMT-0800 (Pacific Standard Time) GUI testing: exposing visual bugs

Mon Dec 28 2009 00:28:14 GMT-0800 (Pacific Standard Time) ABV: Is there a there there?

Sun Dec 27 2009 22:13:53 GMT-0800 (Pacific Standard Time) Improve functional verification quality with mutation-based code coverage

Mon Nov 16 2009 21:09:56 GMT-0800 (Pacific Standard Time) The Use Of Assertions A new study shows the power of seeding your code with assertions

Tue Nov 10 2009 21:14:41 GMT-0800 (Pacific Standard Time) The best of both worlds: Optimizing OCP slave memory behavior

Wed Oct 28 2009 18:24:18 GMT-0700 (Pacific Daylight Time) Why verification engineers are like football players

Thu Oct 22 2009 17:49:17 GMT-0700 (Pacific Daylight Time) FPGA-based rapid prototyping of ASIC, ASSP, and SoC
designs

Mon Oct 19 2009 19:59:48 GMT-0700 (Pacific Daylight Time) FPGA design and verification in mechatronic applications

Sat Oct 17 2009 08:35:46 GMT+0800 Are We There Yet? New Ways to Reduce Verification Time

Thu Oct 08 2009 11:31:00 GMT+0800 Best practices interoperability guide approved for IP
verification

Sat Oct 03 2009 10:25:41 GMT+0800 Using Tcl to create a virtual component in Verilog

Sat Oct 03 2009 10:24:31 GMT+0800 A brief introduction to the TCL Scripting Language

Thu Oct 01 2009 09:05:41 GMT+0800 The Myriad Challenges of Testing Automotive Electronics

Mon Sep 28 2009 22:22:57 GMT-0700 (Pacific Daylight Time) Using CMMI for software requirements testing in system design & development

Mon Sep 28 2009 22:11:15 GMT-0700 (Pacific Daylight Time) Moving model-based development into safety-critical embedded applications

Mon Sep 28 2009 22:09:18 GMT-0700 (Pacific Daylight Time) Using platform independent models to proliferate code across multiple
application environments

Thu Sep 24 2009 20:14:31 GMT-0700 (Pacific Daylight Time) System testing of digital camera devices as reverse
engineering

Sun Sep 20 2009 21:56:55 GMT-0700 (Pacific Daylight Time) OCP-IP SOLV eases SoC verification

Sun Sep 20 2009 21:53:59 GMT-0700 (Pacific Daylight Time) System testing of digital camera devices as reverse
engineering

Tue Aug 18 2009 02:18:26 GMT-0700 (Pacific Daylight Time) Virtual testing with model-based design

Wed Aug 12 2009 22:24:06 GMT-0700 (Pacific Daylight Time) Viewpoint: Capture OCP systems in IP-XACT 1.4

Fri Aug 07 2009 02:53:28 GMT-0700 (Pacific Daylight Time) Visual Modeling of Complex Reactive Systems with Harel UML StateCharts

Mon Jul 27 2009 22:59:56 GMT-0700 (Pacific Daylight Time) Early design verification with virtual system integration and simulation

Mon Jul 27 2009 22:59:13 GMT-0700 (Pacific Daylight Time) Unleash the power of formal technology for CDC verification

Tue Jun 30 2009 21:55:49 GMT-0700 (Pacific Daylight Time) Mentor adds support for control logic to Catapult C

Tue Jun 30 2009 21:55:03 GMT-0700 (Pacific Daylight Time) Forte beefs up high-level synthesis tool

Sun Jun 21 2009 21:44:01 GMT-0700 (Pacific Daylight Time) Managing an adaptive verification environment with OVM

Wed Jun 17 2009 00:19:25 GMT-0700 (Pacific Daylight Time) Learn To Manage All Kinds of Complexity With SystemC

Tue Jun 16 2009 22:15:13 GMT-0700 (Pacific Daylight Time) Get an optimized flow on an AMBA-based design

Sun Jun 14 2009 18:31:37 GMT-0700 (Pacific Daylight Time) Troubleshooting a transaction-level model

Tue Jun 09 2009 21:56:04 GMT-0700 (Pacific Daylight Time) Taking the guesswork out of timing in real-time software
systems

Tue Jun 09 2009 21:50:13 GMT-0700 (Pacific Daylight Time) Model-based design helps aerospace engineers improve design
quality

Mon Jun 01 2009 02:40:57 GMT-0700 (Pacific Daylight Time) Using Algorithmic Synthesis to Design Fourth Generation
Cellular Hardware Accelerators

Mon Jun 01 2009 02:17:20 GMT-0700 (Pacific Daylight Time) Using advanced logging techniques to debug & test SystemVerilog HDL code

Mon May 04 2009 22:02:47 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis: Anesthesia
ventilator evaluation

Mon May 04 2009 22:02:14 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis - Defining a
Profile

Mon May 04 2009 22:01:02 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis - The basics

Mon May 04 2009 21:49:16 GMT-0700 (Pacific Daylight Time) Visualizing, Analyzing and Debugging SystemVerilog
Testbench Environments

Mon May 04 2009 21:47:51 GMT-0700 (Pacific Daylight Time) Using OCP and Coherence Extensions to Support System—Level
Cache Coherence

Thu Apr 23 2009 22:17:43 GMT-0700 (Pacific Daylight Time) No Government Bailout for Poor Test Planning

Tue Apr 21 2009 12:50:27 GMT+0800 (China Standard Time) Hardware Design Requires Hardware Design Languages

Sun Apr 19 2009 22:26:17 GMT-0700 (Pacific Daylight Time) Cornering Those Corner Case Bugs: Functional Coverage On
Multiple Interfaces

Sun Apr 19 2009 22:22:17 GMT-0700 (Pacific Daylight Time) Finding defects using Holzmann's "Power of 10" rules for writing safety critical
code

Sun Apr 19 2009 22:20:21 GMT-0700 (Pacific Daylight Time) What you need to know about automated testing and simulation

Tue Apr 14 2009 13:06:25 GMT+0800 (China Standard Time) Using finite state machines to design software

Tue Apr 14 2009 13:03:38 GMT+0800 (China Standard Time) SOFTWARE TOOLS: New suite provides End-to-End Software
Verification

Tue Apr 14 2009 13:02:51 GMT+0800 (China Standard Time) Overcome LTE PHY challenges using ESL design

Sun Mar 29 2009 22:09:59 GMT-0700 (Pacific Daylight Time) Design quality enhances company survival
Like it or not, semiconductor design in the early 21st century has more in
common with an assembly line than a research lab. That they function smoothly is only possible because manufacturing engineers
know, in advance, exactly how they define quality, and they continuously monitor
and correct quality problems, at the source. This continuous monitoring is often
labeled continuous quality control (CQC). Closed-loop and group-wide feedback must be a non-negotiable component of any
practical CQC process. The broader your range of regressions, the better you will control your design
program. But consider also the personal benefits to a design team lead or manager. Executives value managers who are clearly in control even, paradoxically, if
their projects are not always successful. They know that, over the long haul,
disciplined managers deliver better results on average than their peers.

Fri Mar 20 2009 23:37:20 GMT+0800 A SystemC-Based RTOS Model for Multiprocessor Systems-on-Chips

Mon Mar 02 2009 21:16:29 GMT-0800 (Pacific Standard Time) Functional qualification: a technical brief

Mon Feb 16 2009 18:09:19 UTC+0800 Mentor Graphics inFact Tool provides plug-and-play interoperability with OVM

Mon Feb 16 2009 18:08:43 UTC+0800 ESL: Where are we and where we are going

Mon Feb 16 2009 18:08:11 UTC+0800 Abstraction and Control-Dominated Hardware Designs

Wed Feb 4 2009 15:16:50 UTC+0800 How SLEC improves functional verification

Thu Jan 22 2009 18:14:59 UTC+0800 Mentor unveils TLM 2.0 design flow

Tue Jan 20 2009 15:05:57 UTC+0800 The Virtual Vehicle: Part 1 - In-vehicle networking simulation and analysis

Tue Jan 20 2009 15:04:57 UTC+0800 Architecting the OCP uVC verification component

Tue Jan 20 2009 15:04:29 UTC+0800 Doing ESL system validation using transactors

Tue Jan 20 2009 15:03:38 UTC+0800 An application modeling & hardware description for network-on-chip benchmarking

Tue Dec 23 2008 18:01:02 UTC+0800 Using requirements based testing to find defects in your software builds

Sun Dec 14 2008 21:11:14 UTC+0800 Adapt standard tests to non-standard devices: Automotive qualification of a MEMS-based sensor system

Thu Nov 27 2008 13:14:44 UTC+0800 Unified Verification for Hardware and Embedded Software Developers

Sun Nov 9 2008 08:19:58 UTC+0800 Borrowing from software to use SystemVerilog test bench debug & analysis

Thu Aug 28 2008 12:34:53 UTC+0800 Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions

Wed Aug 27 2008 12:46:40 UTC+0800 TCL Drives C Drives SystemVerilog - An Overview

Wed Aug 27 2008 12:46:49 UTC+0800 Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation - The Details

Tue Aug 26 2008 20:40:04 UTC+0800 Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor

Introduction to and Regression Test for OCP System介绍了TLM、OCP-IP、Channels、Regression Test等概念，值得一读。

Accelerating Functional VerificationCadence的GUI功能验证工具。

Verification Horizons A QUARTERLY PUBLICATION OF MENTOR GRAPHICS Q4 '07 - VOL. 3, ISSUE 4OVM提出以来，Mentor的第一批文章。

I Know What You Didn't Verify Last Summer!

The Great EDA Cover-up

Cadence makes logic verification OVM-savvy

A revolution in functional verification

Applying Constrained-Random Verification to Microprocessors

Efficient testbench implementation for verification proposed by Synopsys staffer

Verification Platform for Complex Designs

Open Verification Methodology ready for download from Cadence, Mentor

Why we need an analog design flow that's like digital now

验证计划报表工具VMM Planner

Commentary: 'Open' is (not) just a four-letter word the meaning of open.

VMM application packages: the next level of productivity

Tue Feb 19 2008 14:09:45 UTC+0800 Mentor Delivers Higher Verification Intelligence

Tue Feb 26 2008 18:23:09 UTC+0800 Multi-language Functional Verification Coverage for Multi-site Projects

Wed Mar 5 2008 13:12:10 UTC+0800 Imperas donation forms open-source virtual platform initiative something like many a virtual machines, but open and free.

Tue Mar 18 2008 13:57:59 UTC+0800 FPGA设计的验证技术及应用原则，非常好的时序仿真指导原则。在以往的调试中我极力回避时序仿真，可以从这篇文章中借鉴一下时序仿真的操作！

Applying incremental simulation techniques

Host Bus Adapter (HBA) Verification with Trek

Sun May 18 2008 20:35:14 UTC+0800 Accellera Forms Verification Standards Committee 验证方法学的“三足鼎立”时代即将结束。

Wed Jun 11 2008 22:50:58 UTC+0800 Performance Improvements with New Secure IP and FAST Simulation Mode Models

Sat Jun 14 2008 08:18:25 UTC+0800 Bridging the Gap Between Silicon and Software Validation

Sat Jun 14 2008 08:51:31 UTC+0800 Protocol stack testing for LTE

Sat Jun 14 2008 08:54:34 UTC+0800 Leveraging Design Insight for Intelligent Verification Methodologies

Sat Jun 14 2008 08:55:13 UTC+0800 OneSpin announces SVA solution for gap-free verification

Wed Jun 18 2008 18:32:55 UTC+0800 Closing the Loop in Testbench Automation

Sun Jun 29 2008 19:56:08 UTC+0800 Static Checks for Power Management at RTL

Thu Aug 14 2008 22:56:20 UTC+0800 Learning not to fear PCI Express compliance Fear is the mind killer.

Assertion分类：

Assertion Based Verification

Set of assertions serves multiple tools

OVL Made Easy for Assertion-Based Verification

Accellera Assertion Technical Committee

Assertions in Verilog

How assertions can be used for design

Viewpoint: Boost verification accuracy with low-power assertions

相关链接：OVM World：Open Verification Methodology

Verification Guild: Forums