Design reviews are very important to the FPGA design process. Reviews should be multidisciplinary and include mechanical and software engineers in addition to hardware and FPGA engineers. The requirements review should be thorough but not overly formal. The objective of the review is the make sure that everyone is aware of the requirements from the earliest stages of the design to avoid design rework later in the design cycle. The following lists provide a summarized list of those objectives, factors and topics relevant to a design review.
Design Review Objectives
Present and discuss design requirements and requirement updates since last official design review with the entire design team.
Present how critical and difficult design requirements and objectives are being met and alternative implementations which were evaluated.
Reviews are critical to catching design issues that may be problems in the future. A project without enough time to prepare for and hold reviews will likely encounter unnecessary delays.
Design Review Factors
Present current design status, design updates, decision, current architecture, updated requirements
Consider full or partial verification matrix or table to present how critical design requirements are being met
Should include block diagrams
Record, track and resolve issues identified during the review
Identify critical design issues and challenges (risk)
Focus on high-risk circuit, function and interface implementations
Present critical Finite State Machines (FSMs)
Identify signals targeted for global resources
Detailed clock implementation overview
Focus on synchronous design implementation
Highlight any unable to be avoided asynchronous circuitry; focus extra design review on this functionality
Review all critical design interfaces and clock domain boundaries (resynchronization)
How high-speed signals and buses will be resynchronized at the FPGA I/O blocks
Present power and thermal estimates
Present mechanical considerations (device size and height, likely number of board layers, proposed access to FPGA configuration and test headers in deliverable product configuration, clearances for device rework)
Power-on reset approach
Design power-up sequence, timing and how all I/O power-up, configuration and reset states will interact with the board-level circuitry
I/O signals requiring special configuration (level, slew, threshold, termination)
Design fault, error and alarm monitoring and response
Design configuration control plan and procedure
Design integration plan (device-level and board-level)
Initial board power-up plan (proposed FPGA minimum functionality)
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