1 准备PIPE IN/OUT的Shell脚本。
删除空白行:sed '/^ *$/d' <oldFile> > <newFile>
2 电路图导出CDL网表
si -batch -command netlist
pipo.exe -h半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS' X1 Y5 m# f% D% [
Usage: pipo Translator SetupFile
2 H) e8 a! g- G; ^# c1 qMicroE.CN::微电中国网 Translator = strmin, cifin
3 \# O7 g; c4 r9 e; o* n: Z owww.microe.cn strmout, cifout
( @* v; x- R1 v; h5 H* @# Q半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS strmtechgen, ciftechgen. p6 M* G$ Z' ~' L% N3 u
' T- E/ E I E4 w k4 |, l7 ~=>半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS 比如:pipo cifout cifFilewww.microe.cn) a# P& X! D& U( p" S+ B+ Q
pipo strmout gdsFile=>半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS \& k- s7 T1 K# A' E2 m( h. f
1 C( R: o; j, N/ n
也可如: pipo strmout strmout.cfg 此时需要配置 strmout.cfg
9 ^: E0 L1 F1 v' p9 ?www.microe. si.exe -help半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS- I$ {- I5 e% O, L b1 {* ?
Usage: si [run directory] [-batch [-command commandName]]半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS8 g- J' T; O6 N
[-difftest] [-noenv] [-cdslib path]
3 关于BUF,DLY,INV的Footprint的使用情况
FAQ: How do you set buffer footprint working in FE IPO?
Follows the methods for setting footprint in FE:
1. If the .lib file being used has:
in_place_swap_mode : "match_footprint"
set, then footprint information needs to be defined for the cells in the library; else no cells will be swapped or inserted during IPO.
However, if the "in_place_swap_mode" variable is not set, footprint information is not required. FE will set default footprint names on cells based on functionality.
2. Follows the other way to set up a footprint environment correctly.
- Dump the footprint info extracted automatically by FE with "reportFootPrint -outfile <footPrint.rpt>"
- Edit the footprint file so that buffers and delay cells belong to different footprints.
- Load the edited footprint info by "loadFootPrint -infile <footPrint.rpt>".
set rda_Input(ui_gen_footprint) {1}
SocEncounter 6.2
Run footprintless flow,command:
set dbgGPSAutoCellFunction 1,
no need setBufFootPrint, setInvFootPrint, or setDelayFootPrint.
SocEncounter 7.1 default support footprintless flow
4 **ERROR: (SOCCK-643): The MinDelay in the clock tree specification file is too big.
Solution:
CTS will report this error when the MinDelay is set to a value greater than 50ns.
This safe guard is in place to prevent huge buffer trees from being inserted. It is
a hard coded value and cannot be changed.
5 How to fix proces Antenna?
setNanoRouteMode -routeInsertAntennaDiode true
# Set the following if a cell with "CLASS CORE ANTENNACELL" is not defined in
the LEF
# setNanoRouteMode -routeAntennaCellName
# Set the following to output file(s) with a list of the diode instances
inserted. One file is created for each diode insertion pass.
# setNanoRouteMode drouteAntennaEcoListFile fileName
# To allow diode insertion on clock nets set the following
# setNanoRouteMode -routeInsertDiodeForClockNets true
routeDesign
see the section "Calculating and Fixing Process Antenna" Violations in the "LEF/DEF
Language Reference."
- For additional options on controlling process antenna fixing see the command
"setNanoRouteMode" in the
"Encounter Command Reference."
- The command verifyProcessAntenna can be used to check for process antenna violations
anytime after the design
is routed.
半导体,微电子,集成电路,IC,工艺,设计,器件,封装,测试,MEMS9 m6 N5 [2 e j$ Y# \$ T# W/ L) A
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