原创 VHDL/VGA视频显示单点

--VHDL/VGA视频彩条显示
--rainsy
--2009,9,18
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity vga2 is
 port(clk : in std_logic;
      rgb : out std_logic_vector(2 downto 0);
    hs  : out std_logic;
      vs  : out std_logic
  );
end;

architecture one of vga2 is
 signal clk25m : std_logic;--像素扫描时钟
 signal hcnt   : std_logic_vector(9 downto 0);--行计数器
 signal vcnt   : std_logic_vector(9 downto 0);--场计数器
begin
 process(clk)
 begin
  if rising_edge(clk) then
   clk25m<=not clk25m;
  end if;
 end process;
 
 process(clk25m)
 begin
  if rising_edge(clk25m) then
   if hcnt="800" then
    hcnt<=(others=>'0');
    if vcnt="525" then
     vcnt<=(others=>'0');
    else
     vcnt<=vcnt+1;
    end if;
   else
    hcnt<=hcnt+1;
   end if;
  end if;
 end process;
 
 process(hcnt,vcnt)
 begin
  if (hcnt>656)and(hcnt<752) then
   hs<='0';--行消隐
  else
   hs<='1';
  end if;
  if (vcnt>489)and(vcnt<492) then
   vs<='0';--场消隐
  else
   vs<='1';
  end if;
 end process;
 
 process(clk25m)
 begin
  if rising_edge(clk25m) then
   if (hcnt<640)and(vcnt<480) then
    if (vcnt=100)and(hcnt=100) then--在坐标(100,100)
     rgb<="111";
    else 
     rgb<="000";
    end if;
   else
    rgb<="000";
   end if;
  end if;
 end process;
end;