SPI Structure

The basic structure of the SPI is shown in right image. The master IC and the slave IC are tied with three signal lines, SCLK (Serial Clock), MISO (Master-In Slave-Out) and MOSI
(Master-Out Slave-In), and contents of both 8-bit shift registers are
exchanged with the shift clock driven by master IC. Additionally an SS
(Slave Select) signal other than above three is used to synchronize
start of packet or byte boundary, and for realize multi-slave
configuration simultaneously. Most slave ICs assign different pin
names, such as DI, DO and CS, to the SPI interface. For one-way
transfer deivce, such as DAC and single channel ADC, either of data
lines may be ommited. The data bits are shifted in MSB first.

When attach some slave ICs to an SPI, the slave ICs are attached
parallel and CS signals from master IC are tied to each slave ICs. The
data output of slave IC that selected by CS signal is enabled and
deselected devices are disconnected from MISO line.

SPI Transfer Timing

SPI Mode	Timing Diagram
Mode 0 Positive Pulse. Latch, then Shift.
Mode 1 Positive Pulse. Shift, then Latch.
Mode 2 Negative Pulse. Latch, then Shift.
Mode 3 Negative Pulse. Shift, then Latch.

In SPI, data shift and data latch are done opposite clock edges
respectively. There is an advantage that when shift and latch
operations are separated, critical timing between two operations can be
avoided. Therfore timing consideration for IC design and board design
can be relieved. But on the other hand there are four operation modes
due to combination of clock polarity and clock phase, master IC must
configure its SPI interface as an SPI mode that slave IC required.