原创 写verilog程序时提高硬件意识

reg q;

always @ (posedge clk)
  q <= d;

reg q;

always @ (posedge clk or posedge reset)
  if (reset)
    q <= 1'b0;
  else
    q <= d;

reg q;

always @ (posedge clk)
  if (reset)
    q <= 1'b0;
  else
    q <= d;

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
  q <= d;

reg q;

always @ (posedge clk)
  if (enable)
    q <= d;

reg q;

always @ (negedge clk)
  q <= d;

reg q;

always @ (q or enable)
   if (enable)
      q = d;

reg y;

always @ (a or b or select)
   if (select)
      y = a;
   else
      y = b;

Two input multiplexer (using ternary operator ?

wire t = (select ? a : b);

reg w;

// mux version 3
always @ (a or b or select)
   case (select)
      1'b1 : w = a;
      default : w = b;
   endcase

reg p;

// mux version 4
always @ (a or b or select)
   begin
   p = b;
   if (select)
      p = a;
   end

reg q;

always @ (a or b or c or select2)
   if (select2 == 2'b00)
      q = a;
   else 
      if (select2 == 2'b01)
         q = b;
      else
         q = c;
 

reg r;

// Priority encoded mux, version 2
always @ (a or b or c or select2)
   begin
   r = c; 
   case (select2)
      2'b00: r = a;
      2'b01: r = b;
   endcase
   end
 

reg s;

always @ (a or b or c or select2)
   begin
   case (select2) // synopsys parallel_case
      2'b00: s = a;
      2'b01: s = b;
      default: s = c; 
   endcase
   end