原创 Error: Top-level design entity "verilog_first" is undefined

Question： Quartus Ⅱ 软件抛出 Error: Top-level design entity "verilog_first" is undefined

Analysis：所建模块名称和顶层文件名称不一致 导致Error出现。如图所示：

                  错误提示：Error: Top-level design entity "verilog_first" is undefined.

                

Solution：将“模块名和顶层文件名“”改一致，再次编译运行即可！