原创 【数字IC】高级数字 IC 设计（7）基于 PE 的脉动阵列设计

Plaintext
module PE(
clk,
rst_n,
ina,
inb,
outa,
outb,
outc
);
parameter SIZE = 8;
input clk,rst_n;
input [SIZE-1:0] ina,inb;
output [SIZE-1:0] outa,outb;
inout [SIZE-1:0] outc;
reg [SIZE-1:0] sumc,outa,outb;


always @ (posedge clk) begin
if(!rst_n)begin
outa <= 0;
outb <= 0;
end
else begin
sumc <= outc + (ina * inb);
outa <= ina;
outb <= inb;
end
end //


assign outc = sumc;


end // always