原创 Performing a Functional Simulation with the ModelS

 2011-3-5 22:15  1585 6 6 分类: 工程师职场

http://quartushelp.altera.com/current/master.htm#mergedProjects/eda/simulation/modelsim/eda_pro_msim_func_sim.htm

You can use the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components with the ModelSim-Altera interface, or with command-line commands.

Note: Do not compile any of the simulation model files in the quartus/eda/sim_lib directory. Simulation libraries for ModelSim-Altera are precompiled.

To perform a functional simulation with the ModelSim-Altera interface:

If you have not already done so, set up a project with the ModelSim-Altera software.
To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench):

On the Compile menu, click Compile.
In the Library list of the Compile Source Files dialog box, select the work library.
In the File name list, type the directory path and file name of the .v file or .vhd file.

or

In the Files of Type list, select All Files (*.*), and in the Look in list select the .v file or .vhd file.

Note: If you have generated a VHDL Output File (.vho) or Verilog Output File (.vo) for use in a functional simulation, you should compile it before proceeding.

Click Compile.
Repeat steps 2b to 2d to compile the testbench file(s).
Click Done.

To load the design:
1. On the Simulate menu, click Simulate.
2. If you are simulating a Verilog HDL design, to specify the ModelSim-Altera precompiled libraries:
  1. Click the Libraries tab.
  2. In the Search Libraries (-L) box, click Add and select the appropriate libraries.
  3. Click OK.
3. In the Name list, click the + icon to expand the work directory.
4. Select the top-level design file to simulate.
5. Click Add.
6. Click Load.
Perform the functional simulation in the ModelSim-Altera software.

Important: If your design contains the alt2gxb megafunction, refer to the appropriate megafunction topic for required settings information.

To perform a functional simulation with command-line commands:

To use the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components using command-line commands:

If you have not already done so, set up a ModelSim-Altera project with command-line commands.
To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench), type the following commands at the ModelSim prompt.

For VHDL designs:

vcom -work work <design name>.vhd vcom -work work <testbench>.vhd

For Verilog HDL designs:

vlog -work work <design name>.v vlog -work work <testbench>.v
To load the design, type the following commands at the ModelSim prompt.

For VHDL designs:

vsim work.<top-level design entity>

For Verilog HDL designs:

vsim -L altera_mf_ver -L lpm_ver.<top-level design entity>
Perform the functional simulation in the ModelSim-Altera software.

Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim-Altera main window into a text file and name the file with a .do extension (that is, <file name>.do).Use this script to recompile the libraries if you update them.

To run a macro script:

From the Mentor Graphics ModelSim main window, click Execute Macro.
In the Execute Do File dialog box, locate your ModelSim macro file (.do).
Click Open.