原创 So what's Cortex

The ARM Cortex family is a new generation of processor that provides a standard architecture for a wide range of technological demands. Unlike the other ARM CPUs, the Cortex family is a complete processor core that provides a standard CPU and system architecture.  The Cortex family comes in three main profiles: the A profile for high end applications, R for real time and M for cost-sensitive and microcontroller applications. The STM32 is based on the Cortex-M3 profile, which is specifically designed for high system performance combined with low power consumption. It has a low enough cost to challenge traditional 8 and 16-bit microcontrollers. 

         Cortex系列是ARM公司新一代的处理器内核，旨在为当前对技术的要求日渐广泛的市场提供一个标准的处理器架构。和其他ARM处理器不一样的是，Cortex系列处理器作为一个完整的处理器核心，在向我们提供标准CPU的同时，还提供了标准的系统架构。Cortex系列分为3个分支：专为高端应用场合而设的“A”（Application）分支，专为实时应用场合而设的“R”（Real-time）分支，还有专为对成本敏感的微控制器应用场合而设的“M”（Microcontroller）分支。STM32基于Cortex-M3分支，专为实现高系统性能与低功率消耗并存而设计。同时它足够低廉的价格也向传统的8位和16位微控制器发起了有力的挑战。

        While the ARM7 and ARM9 CPUs have been successfully integrated into standard microcontrollers, they do show their SoC heritage. This is particularly noticeable in the area of exception and interrupt handling, because each specific  manufacturer  has  designed  their  own  solution.  The  Cortex-M3  provides  a  standardised microcontroller core which goes beyond the CPU to provide the entire heart of a microcontroller (including the interrupt system,
SysTick timer, debug system and memory map). The 4Gbyte address space of the Cortex-M3 is split into well-defined  regions  for  code,  SRAM,  peripherals  and  system  peripherals.  Unlike  the  ARM7,  the  Cortex-M3  is a Harvard architecture and so has multiple busses that allow it to perform operations in parallel, boosting its overall performance. Unlike earlier ARM architectures, the Cortex family allows unaligned data accesses. This ensures the most efficient use of the internal SRAM. The Cortex family also supports setting and clearing of bits within two 1Mbyte regions of memory by a method called bit banding. This allows efficient access to peripheral registers and flags located in SRAM memory without the need for a full Boolean processor.

        随着ARM7和ARM9处理器被成功的整合进标准微控制器里，它们也展示了它们各自特有的产物：SoC（片上操作系统）。特别的，在对异常和中断的响应处理上，我们会更容易看到它们之间的区别，因为每家芯片制造商都有属于自己的一套解决方案。Cortex-M3提出标准化的微控制器核心，在CPU的基础上又提供了整个微控制器的核心部分（包括中断系统，系统节拍时钟，调试系统以及存储区映射）。Cortex-M3内部的4Gbyte线性地址空间被分为Code区，SDRAM区，外部设备区以及系统设备区。和ARM7不同，Cortex-M3基于哈佛体系，拥有多重总线，可以进行并行处理，因而提升了整体性能。同时也和早期的ARM架构不同，Cortex系列处理器允许数据非对齐存取，这能确保内部SDRAM能够得到有效的利用。Cortex系列处理器可以使用一种称为Bit-banding（译为“位带”）的技术，利用两个1Mbyte大小的内存区域实现对“位”的置位和清除。这样就可以有效地对设备寄存器和位于SRAM中的某些标志位提供存取接口，而不再需要完整的布尔逻辑运算过程。

        One of the key components of the Cortex-M3 core is the Nested Vector Interrupt Controller (NVIC). The NVIC provides a standard interrupt structure for all Cortex based microcontrollers and exceptional interrupt handling. The NVIC provides dedicated interrupt vectors for up to 240 peripheral sources where each interrupt source can be individually prioritised. The NVIC has been designed for extremely fast interrupt handling. The time taken from receiving an interrupt to reaching the first line of code in your service routine is just twelve cycles. This is achieved
in  part  by  automatic  stack  handling  which  is  done  by  microcode  within  the  CPU.  In  the  case  of  back  to  back interrupts, the NVIC uses a “tail chaining” method that allows succe-ssive interrupts to be served with only a six cycle latency.  During  the  interrupt stacking phase,  a  high  priority  interrupt can  pre-empt a  low  priority  interrupt without  incurring  any  additional  CPU  cycles.    The  interrupt  structure  is  also  tightly  coupled  to  the  low  power
modes within the Cortex-M3 core. It is possible to configure the CPU to automatically enter a low power on exit from an interrupt. The core then stays asleep until another exception is raised.