原创 FPGA 写数据到USBslavefifo 经testbench验证

module test_slavefifo(
 //input
  clk,
  rst,
 //slavefifo interface
  u_ifclk,
  dataout,   //USB dataout
  u_slwr,  //fifo 的写使能端口  高电平有效
  u_slrd,  // fifo 的读使能端口  高电平有效
  u_sloe,  //USB FIFO 输出使能端口  高电平有效
  
  u_fifoaddr0, //fifo 的选择端口 高电平有效
  u_fifoaddr1,
  
  u_flag  //控制FPGA的数据是否发送，低电平有效
);

input clk,
   rst;
  
input u_flag;

output u_ifclk,
    u_slwr,
    u_slrd,
    u_sloe,   
    u_fifoaddr0,
    u_fifoaddr1;
   
output [7:0] dataout;   
  
reg [7:0]  dataout;
reg [3:0] count=0;
reg
 u_ifclk1=0,
 u_slwr,
&nP>

/*
*  状态机
* 功能： 往USB的fifo中写入数据
*/ 
parameter  IDLE = 'H0,
   WRITE_REDAY ='H1,
   WRITE ='H2;
always @ (posedge u_ifclk)
 begin
  if(!rst)
   begin
    dataout <= 'hffff;
    u_slwr <= 'b0;
    u_slrd <= 'b0;
    u_sloe <= 'b0;
    STATE <= IDLE;
   end
  else
   begin
    case(STATE)
    IDLE:
     begin
      STATE <= WRITE;
     end
    WRITE:
     begin
     if(!u_flag)
      begin
       u_slwr <= 'b1;
       dataout <= dataout + 'b1;
       STATE <= IDLE;
      end
     else
      begin
       u_slwr <= 'b0;
       STATE <= IDLE;
      end
     end
    default:
     STATE <= IDLE;
    endcase
   end
 end
/*生成接口时钟*/
always @ (posedge clk)
 begin
  if(count>=5)
   begin
   count <= 'b0;
   u_ifclk1 <= ~u_ifclk1;
   end
  else
   count <= count + 'b1;
 end

 
/*    fifo的选择端口 选择FIFO8   */ 
assign u_fifoaddr0 = 'b1;
assign u_fifoaddr1 = 'b1;
assign u_ifclk = u_ifclk1;

endmodule