原创 ICT GR228X

<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />MTG ---MXI to GenRad board <?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

Functional blocks are MXI to GR bus interface,

low speed controller, data expander

      模块功能包含:：MXI 到 GR 的内部总线接口, 低速控制器，数据扩展

RTC--- Run Time Controller

BUS interface for the analog subsystem directs &

coordinates pin board activities; data transfers

between cpu and the digital subsystem

       模块功能包括：模拟子系统直接控制和调整pin卡的总线接口，数字子系统和CPU之间的数据转换

CST---Clock/Sync/Trigger board

Provides event timing and event detection

Reference Driver/Sensor reference

Supplies programmed dc reference voltages for the

D/S pin boards

      提供事件定时和事件检测

      提供 Driver/Sensor 的参考

      为D/S pin卡提供可编程的DC参考电压

CFB--- Custom Function Board

DSM--- Deep Serial Memory

AFTM ---Analog Functional Test Module

ICA ---In-Circuit Analog Module

Analog Functional Test Module (AFTM)

模拟功能测试模块

¨ Functionally tests analog networks  模拟功能性测试网络

¨ Measures D/A converters   D/A 转换器测量

¨ Provides frequency response of crystal oscillators   提供晶体震荡频率响应

¨ Performs pulse width measurements  脉冲宽度测量

The AFTM module resides in the pin cage and takes up one driver/sensor slot. When

installed with a DSM board the AFTM will always be in the higher numbered slot after

of the DSM board. The board contains:

AFTM 模块放在pin笼里并占用一个 Driver/Sensor 槽。当同时安装了DSM卡的时候，AFTM 一直都j紧跟在DSM卡后面, 卡包含:

¨ 16 bit DC voltmeter   16位直流电压计

¨ True RMS AC voltmeter  正均方根 交流电压计

¨ 16 Bit sampling voltmeter  16位采样电压计

¨ AC/DC source  AC/DC 源

¨ TTL signal output  逻辑信号输出

¨ Frequency/Timer interval meter 频率/时间 间隔计量器

¨ High frequency scanner   高频率扫描仪

Custom Function Board

The Custom Function board (CFB) provides users the ability to create application

specific hardware to meet their specialized testing requirements. Prior to this board’s

availability, when unique test circuitry was required, hardware had to be built into each

test fixture. Now circuits can be mounted within the test system where these added

resources can be used with a variety of test fixtures.

The CFB, shown in the following figure, occupies one pin board slot and contains four

separate breadboard modules, which provide a convenient location for these custom

hardware resources. The breadboard modules are connected to the receiver pins via a

high frequency (100 MHz) scanning matrix as well as the systems’ analog instruments

via the analog scanning system. GenRad has developed several modules to meet today’s

test requirements.

自定义功能板为使用者提供一个专门为一些特殊测试而增加一些自定硬件和线路的空间。在使用自定义功能板前，有一个很重要的事就是每个需要应用到自定义功能板上的特殊电路测试都必须在夹具上增加一个使用电路。现在系统能在这些补充资源与许多测试设备和夹具使用.

自定义功能板特性如下：占用一个pin卡槽，有4个单独分开的电路区域，为特定的硬件增加提供一个方便的扩展位置，电路板连接到一个具有和系统模拟装置一样的100Mhz扫描的接口。 GenRad已经开发出几个不同的模块来适应今天的测试要求.

TS8X Hardware Overview Training 1 - 17

Deep Serial Memory (DSM)

Extends the test system memory by supplying state data to the driver/sensors via the

digital instrument BUS.

Intended for test applications requiring deep serial vectors that only use a few pins. For

example, boundary scan and proprietary scan techniques, FLASH and In-System

Programming applications.

The DSM board is installed in the highest available pin board slot, except when AFTM

and or ICA boards are installed.

串行深度记忆内存(DSM)

通过数字总线给 Driver / Sensor 提供状态数据来实现对测试系统进行内存拓展。DSM一般只用于边界扫描，proprietary扫描技术，Flash 和 系统内部烧录程序。

DSM卡紧跟在pin卡之后，在装了AFTM 和ICA卡的时候处在最高的位置。

¨ Max system nail count reduced by 128 nails per DSM board 每增加一个DSM卡，系统总针数就减少128支

¨ Controlled with the GR228X Test Language. 用GR228X 测试程序控制

In-Circuit Analog Module

The in–circuit analog (ICA) module resides in the pin cage. This module is composed of two

boards, a top and a bottom board. Operational power for the module (+15, –18, +5 [V CC], +6,

–5.2 [VGE], and ±24 Vdc) is supplied through the pin cage backplane from system power

supplies. The ±24V is supplied from system power supplies. The high–voltage test option

includes a ±150 Vdc power source (a DC/DC converter module external to the ICA module) and a

high–voltage daughter board (resident on the ICA module). An ICA extender board (PN

9004–0410) is available in the optional service kit.

The ICA module provides stimulus and measurement facilities for measuring shorts, opens, and

incorrect component values on the UUT. In–circuit parameter measurements of resistance,

capacitance, and inductance are available to identify component values. Analog functional testing

verifies powered component parameters such as transistor beta, op–amp closed loop gain, diode

characteristics, and transfer function measurements.

Other module resources include direct digital synthesis–based arbitrary waveform generation, full

six–wire measurement capability, synchronous sampling methods of extracting complex

impedance values (for more precise RLC measurements), and a universal (direct digital synthesis

controlled) 16–bit sampling DVM resource. Other features of this module are a high output drive

current of ±500 mA and in–circuit test frequencies ranging up to 100 kHz.

In-Circuit模拟模块

In-Circuit 模拟模块（ICA）安装在pin笼里，这个卡由正面和背面两块板组成。他所需要的电压（+15, –18, +5 [V CC], +6,–5.2 [VGE], and ±24 Vdc）由系统电源通过系统主板提供。±24V是通过系统电源直接提供。在高电压测试选项中包含一个±150 Vdc电压源选项（通过一个外部的DC / DC的变压器输入ICA模块的）和一个高电压的姐妹模块（包含在ICA模块中）.此外，还有一个ICA扩展卡(PN: 9004–0410)为可选板。

ICA模块提供脉冲和测量仪器来测量待测板的短路的开路和不正确的元件参数值。 元件参数测试包括电阻，电容和一些能够可以用辨认的元件参数值的测量。模拟功能测试可以检测上电元件的参数，包括三极管和二极管的特性，转换器功能的测量。

这个模块其他功能包括直接综合的任意波形的产生，完整的6线测试能力，复杂阻抗的同步采样法（为了更精确的测量RLC）和一通用 (直接的数字的合成控制) 16bit 采样DVM源. 此外，还有500ma的高输出驱动和高达100khz的测试频率。

Instrument resources are 

包含的装置包括：

¨ DC voltage source 直流电压源

¨ DC current source 直流电流源

¨ AC source 交流源

¨ AC measurement 交流测量

¨ AC impedance measurement 交流阻抗测量

¨ DC current meter 直流电流表

¨ AC current meter 交流电流表

¨ Waveform digitizer 波形数字转换器

Test functions are for 测试功能为了检测：

¨ Shorts 短路

¨ Opens 开路

¨ Resistance 电阻

¨ Capacitance 电容

¨ Inductance 电感

¨ Transistors 三极管

¨ Diodes 二极管

The following diagram shows a simplified block diagram of the ICA module’s instruments,

sources, and multiplexer. The ICA module is also electrically connected to the nine BNC

connector ports on the INSTRUMENT MULTIPLEXER plate at the rear of the pin bay. This

feature provides the system with the capability, under program control, to connect and operate

external instruments having a digital bus interface compatible with IEEE Standard 488 Digital

Interface for Programmable Instrumentation.

下列是ICA 模块装置的一简化的框图

ICA模块通过多路开关选择器上背面的针槽电气的连接了9个BNC连接口。这样特性使系统可以用程序控制，并提供为连接和操作拓展的装置提供一个数字的总线和一个符合IEEE488标准的数字编程界面。

Two other features of the ICA module are the calibration standards daughter board and the high–

voltage daughter board (option). Both of these boards reside on the ICA module’s bottom board

as shown in the following the diagram.

两个ICA其它特点是校准姐妹板和高压姐妹板。 这两块板都安装在ICA模块的板底， 可以由下图表示：

Lesson 7: Digital Subsystem

第七节： 数字子系统

Overview

总览

The digital subsystem receives command and control instructions from the PC and performs

digital testing of the UUT circuits through the test receiver and UUT test fixture.

The various devices used in the digital subsystem are:

数字子系统通过PC接收指令和控制仪器并通过测试接受器和测试夹具来实现数字电路测试。

在数字子系统中使用的装置有：

¨ MTG board   MTG板

¨ High Speed (HS) controller board 高速(HS)控制板

¨ Clock/sync/trigger (CST) board 时钟 / 同步 / 触发器 （CST）板

¨ Pin boards pin卡

¨ Driver/sensor (D/S) reference board Driver/sensor (D/S) 参考板

Optionally, there are three types of devices associated with the digital subsystem hardware

located in the pin cage. They are pin boards 3 through 30, the Analog Functional Test Module

(AFTM), Deep Serial Memory board (DSM) and Custom Function Board (CFB). A maximum of

one AFTM, two DSM boards and three CFBs can be installed.

The MTG board, HSC board, clock/sync/trigger board, D/S reference board, D/S pin boards, plus

optional AFTM and DSM boards are all located in the pin cage.

在针笼里， 有3种装置可以随意的连接到数字子系统的硬件上。 他们是 3到30 的pin卡，模拟功能测试模块(AFTM), 串行深度记忆内存板（DSM）和自定义功能板（CFB）。 最多只可以安装1 AFTM,2 DSM和 3 CFB.

所有的MTG 板，HSC板, 时钟 / 同步 / 触发器 （CST）板, D/S参考板，D/S pin 板， 加上可选的AFTM和DSM板都是安装在PIN笼内的。

The following diagram is a simplified block diagram for the digital subsystem.

Digital tests of the UUT circuits are managed by the HSC board (in high-speed mode) or the Low

Speed (LS) controller on the MTG board (in standard mode) depending on the test application.

Test patterns (logic levels) are applied to the UUT circuits and the results sensed by D/S circuits

located on the pin boards.

The CST board provides UUT test timing (clocking) and event detection (triggering), also through

the test receiver. Additionally, the CST board interfaces to the HSC board to synchronize testing.

The D/S reference board supplies programmed reference voltages for the pin-board D/S circuits.

Voltages are also supplied to elements of the CST board.

下面是数字子系统的一个简化框图

由测试程序来选者使用MTG板(标准模式下)上的高速控制卡（高速模式）还是低速控制卡（LS）来管理待测板的数字电路测试。测试逻辑信号应用到待测板上，然后由pin卡上的 D/S来接收测试结果。

CST板提供 uut的测试时钟频率（定时）和事件检测（触发器），当然也通过接收器来实现。 另外，CST板到HSC板的接口是同步进行测试的。D/S 参考板为pin 卡的D/S电路提供参考电压，同时也为CST供应运作电压.

MXI-to-GenRad (MTG) Board

¨ Resides in slot 0 of the pin cage. 再pin笼里装在 0 槽

¨ Major functional blocks are the MXI interface, low speed controller, data expander, QAF, and

local MTG support. The QAF bus is not used. 主要的功能模块是 MXI 接口，低速控制器，数据扩展，QAF和本地的MTG支持。QAF 总线并不使用。

MXI Interface

MXI接口

¨ Slave only device. 唯一的附属装置

¨ 32 address lines with 64K address space. 32位地址线 64k的地址空间

¨ 32 data lines, bus supports 16 bit data transfers. 32位数据线 ， 总线支持16位数据转换

Low Speed Controller

低速控制器

¨ Provides the test timing and control functions in the digital subsystem for the pin boards in the

pin cage when slave mode is executed for a low-speed burst operation. 当选定的模式为低速脉冲时，为在pin笼里的品pin卡的数字子系统提供测试时钟和控制功能。

Data Expander

数据扩展器

¨ Interface between the MXI II interface and the digital subsystem. 是MXI II接口与数字子系统之间的一个接口

¨ Receives blocks of PC data and transfers them into the correct memory locations in the

digital subsystem. 从PC得到数据块，并将他们转换到数字子系统中正确的内存位置。

¨ Unpacks or expands the data stored in memory. 解压和扩展储存在内存中的数据

¨ Recognizes programmed I/O data transfers targeted for the digital subsystem and translates

them into bus cycles understood by the digital subsystem. 识别程序的I/O数据并将目标转换成能被数字子系统识别的数据，同时转换成数字系统能识别的总线循环。

Local MTG Support

本地MTG支持

¨ Contains registers that control diagnostic and test functions, miscellaneous control and status

registers, a temperature sensor, and a power-on reset circuit 包含诊断和测试功能寄存器，各种控制和状态寄存器，一个温度感应器和一个电源重起电路。

¨ Temperature sensor circuitry selectively generates an interrupt when a high-temperature

condition occurs. 温度感应电路在感应到高温时将产生一个中断。

High Speed (HS) Controller Board

高速（HS）控制板

The HS controller board (PN 2277–4711) performs as both a bus interface controller during data

transactions with the PC (Load Mode) and as a program sequencer when a high–speed digital

burst is executed (Run Mode). Refer to following diagram.

The HS controller board:

高速控制板(PN 2277–4711)在和PC进行数据传输的时候(Load Mode)相当于一个总线接口的控制器，在高速数字脉冲运行时(Run Mode)高速控制板相当于一个程序序列分析仪。 请参照下面的图表。

HS 控制板包括：

¨ Produces the appropriate bus control and data transfers for digital subsystem I/O

transactions. 为数字子系统的 I/O传输产生适当的总线控制和数据转换。

¨ Receives and stores PC microcode instructions for the digital subsystem. 为数字子系统接收和储存PC指令代码。

¨ Interprets the microcode instructions stored in the opcode memory to control the operation of

the digital subsystem during testing. 再测试过程中解释储存在 opcode 内存的指令代码来执行数字测试。

¨ Produces the memory addresses and D/S control signals required during test execution. 根据测试需要产生内存地址和D/S控制信号。

¨ Responds to signals from the MTG board during slave mode, and produces control signals 响应从在附属模式下的MTG板和产生控制信号

Load Mode

加载模式

¨ Load program microcode into the 16K X 56 bits program sequence memory for the runtime

execution. 再运行的时候加载程序代码到一个16K X 56位的程序顺序内存中。

¨ Interfaces to D/S reference board to setup logic levels for the drivers/sensors. 连接到D/S参考板上的一个接口，为drivers/sensors调整逻辑水平。

¨ Interfaces to CST board to setup for the D/S strobes. 到CST板的接口调整 D/S的的频闪。

¨ Interfaces to pin boards to load test pattern into the 16K X 4 bits D/S memory. 连接到pin卡的接口，加载测试模式到16kX4位的 D/S内存上。

Run Mode

运行模式

¨ Provides address to the CONNECT, STATE, and SENSE-ENABLE memory bits in the pin

board for the burst execution. 在脉冲运行时，提供地址到CONNECT, STATE, 和SENSE-ENABLE 内存位到pin 卡。

¨ Provides pipelined address to the RESULT memory bit in the pin board. RESULT memory bit

is read back to the CPU during debug session. 为pin卡提供RESULT内存位的地址通道。在调试期间RESULT内存位将被cpu读取。

Clock/Sync/Trigger Board

时钟/同步/触发器 板

The CST board (PN 2277–4712)

CST板(PN 2277–4712)

¨ Supplies timing signals for use by the HS controller board program sequencer 为高速控制板的程序序列器提供时钟信号

¨ Produces strobes that activate the pin board D/Ss 产生激活pin卡上D/S的频闪。

¨ Generates four programmable clock waveforms (multiplexed 1:4) for use as clock drivers at

the UUT 为UUT产生4个可编程的时钟波形(复用 1:4)作为uut 的时钟驱动。

¨ Contains event circuitry (match) that monitors the state of up to 15 trigger nails 包含事件电路，可以同时显示15个触发针状态。

¨ Provides a single sync sensor that interfaces a UUT signal to the Phase Lock Loop for clock

synchronization 提供一个单同步感应器连接到UUT信号来实现锁定环路的时钟同步。

Clock and Timing Operation

时钟和定时操作

The function of the four high–speed clock drivers is to develop the specified clock output pulses

that are used to drive circuitry on the UUT. These clock signals are multiplexed, as shown in the

following diagram, and routed through the receiver to the UUT.

4个高速时钟驱动器的功能是产生特定的输出脉冲来驱动UUT上的电路。这些时钟信号是复用的，请看下面的图表，路由后通过接收器到达UUT.

Triggering and Synchronization

触发和同步

The essential function of the trigger circuits is to act as an event detector (look for known output

states) before proceeding to the next step.

The clock sync sensor is designed to interface a UUT clock signal to the CST board phase–lock

loop. The CST board multiplexes the clock sync sensor to one of eight inputs.

触发线路主要的功能是在进行到下一步前相当于一个监测器（寻找已知的输出状态）。时钟同步感应是为了连接UUT时钟信号到CST板锁定环路而设计的。 CST板将时钟同步感应器信号复用到8个输入信号中。

D/S Reference Board

D/S 参考板

The D/S reference board (PN 9004–0406) supplies programmed voltages for: -

D/S参考板(PN 9004–0406)提供可编程电压给:

¨ D/Ss on the pin boards. Pin卡上的D/Ss

¨ Clock drivers, the trigger sensors and sync sensor on the CST board. CST板上有时钟驱动器，触发感应器和同步感应器

The D/S reference board is located in the pin cage. Two logic–level sets (A or B) are available

with a logic–level range of –6V to +10V for the D/Ss. The following diagram is a simplified block

diagram of the D/S reference board.

D/S参考板安装在pin笼里。 两个逻辑标准-6V到+10V可选（A或者B）给D/Ss. 下面是D/S参考板的简单框图：

Functional Description

功能描述

All information to the D/S reference board is transmitted through the HS controller board by the

PC.

A 12–bit data word is received for each reference voltage and stored in memory and stored into

the 32 X 12-bit memory.

The data from the memory is applied to a D/A converter and is converted to a voltage.

Since only one DAC is available, a time multiplex scheme is employed using time multiplex

control circuitry and 32 sample and hold circuitry to capture 32 reference levels from the memory.

所有到达D/S参考板的信息都是通过HS控制板从PC传输过来的。 为每一个参考电压接收到的12位数据都储存在32X12位的内存中。 根据内存的数据通过D/A转换器转换成电压。 当仅仅只有一个DAC可用时，就转为时分复用来控制电路和从内存中抽样32个参考电压并保持这32个参考电压。

NOTE Only 14 reference levels are used.

注意 只有14个参考电压是使用的

DRIVERS/SENSORS:

驱动器/感应器

VILA, VIHA, VOLA, VOLB (A 族)

VILB, VIHB, VOLB, VOHB (B 族)

例如: SET LGC VIHA="5V", VILA="0V", VOHA="2".4V, VOLA="0".8V LVLA (1-128)

SET LGC VIHB="0V", VILB="-2V", VOHB="-0".2V, VOLB="1".8V LVLB (129-256)

CLOCK DRIVERS 时钟驱动器

VCDH, VCDL

例如: SET LGC VCDH="5V", VCDL="0V"

TRIGGER THRESHOLD 触发器 阀值

VTT

Example: SET LGC VTT="2V"

SYNC THRESHOLD 同步 阀值

VCST, VCSH, VCSL

例如: SET LGC VCST=2V, VCSH="6V", VCSL="0V"

Relay Drivers

继电驱动器

1. PIO (0) relay–drivers

  PIO (0) 继电驱动器

- Used as the system control relays that performs dedicated system functions and

operations. 用来作为系统的控制继电器 专门用于系统功能和操作

- Senses test fixture placement and the fixture identification code, which is read back to the

PC. The PC can then select the test program associated with a particular test fixture.

 获得夹具的定位和识别代码， 并传给PC。 PC可以通过获得的信息来为专门的夹具选择测试程序

- Used to drive the relays that actuate the dual vacuum system.

 用来驱动控制双真空系统的继电器

2. PIO (1) relay–drivers

PIO (1) 继电驱动器

- Furnish a relay and TTL drive/sense capability for user control

 为使用者提供继电器和TTL 驱动器/感应器

- Functions in a test fixture or peripheral unit, such as energizing relays, lighting lamps,

sensing switch positions, etc.

在夹具或外部的单元里的功能有很多,例如提供激励 中继,亮灯,感应切换位置,等等.

-          Each relay driver is an open–collector transistor with a suppression diode.

每一个中继驱动器是一个集电极开环的三极管和一个稳压二极管

PIO (0) and PIO (1) each consists a set of: -

PIO (0) 和 PIO (1) 共同的地方有:

- 16 TTL drivers with a high output current of –1.2 mA (sourcing) at 2.4V, and a low output

current at +48 mA (sinking) at 0.4V.

 16个在2.4V时高输出-1.2mA电流和在0.4V时低输出48mA（下沉）电流的TTL驱动器

- 16 TTL sense lines, each of which has a fan–in of one TTL load.

  16个TTL感应线，每一个TTL 负荷都有一个fan–in。

- 6 switch–sense line pairs, with set and reset inputs for single–pole, double–throw (SPDT)

switch debouncing.

 6个开关感应线对，将输入切换成single–pole, double–throw (SPDT)来消除反冲

- Switch–sense lines (per PIO) with a set–only input for a latch capability; resets are

grounded. All sense lines have pull–up resistors to +5V.

 每一个PIO的开关感应线都有一个控制开关的唯一的输入。 重置是接地。所有的感应线都有上拉到+5V的上拉电阻。

Power Status Circuitry

电源状态电路

Monitors inputs received from the pin cage backplane plus an on–board sensor and sends out–

of–tolerance error messages to the PC.

Devices monitored are the pin bay power supplies and a temperature sensor.

监视从pin笼的底板上的一个感应器的输入并将超过界限的电压错误信息传送给PC.

监视装置是针湾电源和一个温度感应器

Fuses on the D/S Reference Board for Other Subsystems

为了其他子系统在D/S参考板上的保险丝

Fuse F5 on the D/S reference board is connected in series between the 15V on the pin cage

backplane and the vacuum subsystem. The vacuum subsystem will be inoperative if this fuse is

open.

Fuse F6 on the D/S reference board is connected in series between the 15V on the pin cage

backplane and the fixed voltage UUT power–supply filter board. This filter board will be

inoperative if this fuse is open.

参考板上的F5保险丝是连接pin笼底板15V和真空子系统保险丝。 当保险丝断时，真空泵将不能正常运作。

参考板上的F6保险丝是连接pin笼底板15V和UUT固定电压源的过滤板。当保险丝断时，过滤板将不能正常运作。

Pin Boards

Pin卡

There are two types of pin boards that can be used:

有两种类型的pin卡可以使用：

- Combo I with 16 D/S circuits (P/N 2277-4020)

  拥有16个D/S电路的Combo I (P/N 2277-4020)

- Combo II with 32 D/S circuits (P/N 2277-4021)

拥有32个D/S电路的Combo II (P/N 2277-4021)

The pin cage cannot contain a mix of the Combo I and Combo II pin boards; they must all be

either Combo I or Combo II.

The pin board’s primary function is to drive or sense logic nodes on a unit–under–test (UUT) at

pre–selected voltage levels.

Combo I 和 Combo II不能混合安装在pin笼里。 他们必须全部是combo I 或者combo II.

Pin卡最主要的功能是驱动和感应连接到待测板（UUT）逻辑针的电压大小。

Combo I

Each Combo I pin board contains 16 D/S circuits and a relay multiplexer that can connect each

D/S to any of 16 different test nails (16 D/Ss per board multiplexed 2:16 for a total of 128 pins).

每一个combo I 卡包含有16个D/S电路和复用继电器，每一个D/S可以同时连接16个不同的测试针（每一个板上16个D/S可以2:16复用，一共可以支持128个针）

Combo II

Each Combo II pin board contains 32 D/S circuits and a relay multiplexer that can connect each

D/S to any of eight different test nails (32 D/Ss per board multiplexed 2:8 for a total of 128 pins).

Additionally, each D/S circuit can be connected to eight analog measurements lines (channels A

through H).

Other hardware features include a Parallel CRC generator to compute Cyclical Redundancy

Checks from any or all sensors, and an external digital instrument bus with access to the D/Ss.

每一个combo II 卡包含有32个D/S电路和复用继电器，每一个D/S可以同时连接8个不同的测试针（每一个板上32个D/S可以2:8复用，一共可以支持128个针）

此外，每一个D/S电路可以连接8个模拟测量通道（A到H通道）

其他硬件的特性包括一个并行的CRC产生器去计算冗余循环。 检查每个感应器和连接到感应器的扩展的数字装置总线。

DRIVER/SENSORS

Each driver/sensor in the pin board has 16K X 4 bits of memory namely:

每一个pin卡上的driver/sensor都有一个16kX4位的内存： -

CONNECT, STATE, SENSE-ENABLE AND RESULT

CONNECT (CON) = 1 (Driver)

CONNECT (CON) = 0 (Sensor)

STATE (STA) = 1 (Drive or sense HI depends on CON bit)

STATE (STA) = 0 (Drive or sense LO depends on CON bit)

SENSE-ENABLE (SEE) = 1 (Enable sensed data; enable failure)

SENSE-ENABLE (SEE) = 0 (Disable sensed data; ignore failure)

RESULT (RES) = 1 (Sensed data is HI)

RESULT (RES) = 0 (Sensed data is LO)

Functional Description

功能描述

Before a burst is executed, the test vectors (pattern) are loaded into the CON, STA, and SEE

memory bits for each driver/sensor.

During execution of the burst, the high-speed controller (HSC) applies a 14 bits address (16K) to

the memory bits, which latches the test vector to the D/S circuits.

A precisely timed driver strobe from the HSC (originates from the CST board) causes the D/S to

assume the state set by the test vector and outputs to the DUT.

The arrival of the sense strobe from the HSC samples the output of the sense comparators.

When the senses data state is different from the programmed (expected) state, an error data is

latched and returned to the HSC to determine program flow; branch on error, ignore error or fail

state etc.

The sensed output state is also stored in the result memory bit (RES) for failure log and

waveform display during debug session.

每一个脉冲运行前，每个driver/sensor都将测试矢量加载进CON, STA, 和 SEE内存位。

在执行脉冲时，高速控制卡将锁村起来的D/S电路的14位地址(16K)的测试矢量到内存位。

从HSC板来的一个精确的时钟驱动频闪（发源于CST板）使D/S将测试矢量的状态表现出来并输出到DUT.

从HSC抽样出来的感应信号都是通过感应放大器放大后的信号。

当感应到的数据和所预期的不同的时候，错误数据将被锁存并返还到HSC去决定 转移搓去 忽略错误或者错误状态 等等。

在调试阶段，感应器输出的的状态也被储存在结果内存位（RES），包括错误纪录和波形。

System Test Program

系统测试程序

Overview

总览

The System Test Program is a series of test programs that form a single-testing sequence.

You can also select and run any individual test.

This diagnostic is structured into two user-selectable modes on the SYSTEST dialog box.

They are:

系统测试程序是由单个测试步骤形成的一系列的测试程序。 当然你也可以选者运行任何一个单独的测试。 在系统自检框里有两个可选的模式，他们是：

¨ STANDARD Test Resolution Mode 标准测试分析模式

¨ DIAGNOSTIC Test Resolution Mode 诊断测试分析模式

System devices and subsystems tested with the System Test Program include the:

系统测试程序对于系统装置和自系统测试包括：

¨ MXI-To-GenRad (MTG) Board MXI-To-GenRad (MTG)板

¨ Analog Subsystem 模拟子系统

¨ Digital Subsystem 数字子系统

¨ CRT Monitor CRT显示器

¨ Keyboard and Keypad 键盘和按键

¨ UUT Power Supplies UUT电源

¨ Vacuum Controls 真空泵控制

¨ Analog Functional Test Module (AFTM) 模拟功能测试模块(AFTM)

¨ Deep Serial Memory Module (DSM) 串行深度内存模块

STANDARD Test Resolution Mode

标准测试分析模式

Tests executed in the STANDARD Test Resolution mode from the SYSTEST dialog box are

the first system verification tests that should be executed.

标准测试时系统扫描测试中应该第一步执行的测试在系统自检对话框中。

DIAGNOSTIC Test Resolution Mode

诊断测试分析模式

This mode provides powerful diagnostic flexibility for GenRad-manufactured devices. The first

level enables you to test individual subsystems. The second level enables you to select in-depth

tests for individual devices. In addition, you can select individual tests to form a diagnostic test

sequence used to determine the fault location.

这个模式为GenRad生产的装置提供有力的灵活的分析。 初级的测试可以使你测试每个单独的子系统。 第二级可以使你选择更深入的测试对每个装置。 另外， 你可以选者单独的测试模式去分析错误的区域.