【yadog原创】Tcl+Modelsim简明操作教程<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
本文的例子基于一个非常常见的时钟分频的工程，分频采用计数器实现。
本文的目的不在于如何写分频器，也不在于如何建立Modelsim工程，而在于如何使用Tcl控制Modelsim仿真！
本文的编程语言为Verilog。
一、准备工作
1. 设计源文件clk_div.v。
思路很简单，对输入信号使用计数器方式进行分频。
输入以下代码，保存文件为clk_div.v。源码如下：
/**************************************************************************
* Copyright (c) 2008 YADOG
* All rights reserved
* Pls keep this header anywhere,anytime
* Any question,pls feel free to contact
* yadog@163.com
*-----------------------------------------------------------------------------
* Title : module for frequency division project
* Project : demo for using tcl in modelsim
*-----------------------------------------------------------------------------
* File : clk_div.v
* Author : yadog (yadog@163.com)
* Organization: PRIVACY
* Created : 2009/03/14
* Last update : 2009/03/14
* Platform : STRATIX II GX
* Simulators : Modelsim se 6.4/WindowsXP
* Synthesizers: QII 8.1/WindowsXP
* Language : Verilog-2001/2005
* Target :
* Dependency :
*-----------------------------------------------------------------------------
* Description: This is a module for frequency division project.
* It has a single module:
* ----clk_div.v
* use a counter to divide frequency
*-----------------------------------------------------------------------------
*pin assign : PIN_N2 --clk_Sys;
* PIN_C2 --reset
*-----------------------------------------------------------------------------
* Revision History:
*-------------------
* Revision Number : 1
* Version : 1.0
* Date : 2009/03/14
* Modifier : yadog@163.com
* Desccription : Created
* Known bugs :
* To Optimze :
*-----------------------------------------------------------------------------
******************************************************************************/
module clk_div (
input clk_in, //frequency to be divided
input reset_n, //asynchronous,negedge active
output reg clk_out //output
);
reg [9:0] j;
//------------------------Frequency Didiver-----------------------------
//use a 10-bit up counter
always @(posedge clk_in,negedge reset_n)
if(!reset_n) //negedge trig,asynchronous reset
begin
clk_out <= 1'b0;
j <= 10'b0;
end
else
begin
if(j==10'd23) //here use 24(Note--divider is 48),you can change to any 10-bit number
begin
j <= 10'd0;
clk_out <= ~clk_out;
end
else
begin
j <= j + 1'b1; //up counter
end
end
endmodule
2. modelsim仿真文件clk_div_tb.v。
输入以下代码，保存文件为clk_div_tb.v。源码如下：
/******************************************************************************
* Copyright (c) 2008 YADOG
* All rights reserved
* Pls keep this header anywhere,anytime
* Any question,pls feel free to contact
* yadog@163.com
*-----------------------------------------------------------------------------
* Title : modelsim testbench for frequency division project
* Project : demo for using tcl in modelsim
*-----------------------------------------------------------------------------
* File : clk_div_tb.v
* Author : yadog (yadog@163.com)
* Organization: PRIVACY
* Created : 2009/03/14
* Last update : 2009/03/14
* Platform : STRATIX II GX
* Simulators : Modelsim se 6.4/WindowsXP
* Synthesizers: QII 8.1/WindowsXP
* Language : Verilog-2001/2005
* Target :
* Dependency : clk_div.v
*-----------------------------------------------------------------------------
* Description: This is a modelsim testbench for frequency division project.
*-----------------------------------------------------------------------------
*pin assign : PIN_N2 --clk_Sys;
* PIN_C2 --reset
*-----------------------------------------------------------------------------
* Revision History:
*-------------------
* Revision Number : 1
* Version : 1.0
* Date : 2009/03/14
* Modifier : yadog@163.com
* Desccription : Created
* Known bugs :
* To Optimze :
*-----------------------------------------------------------------------------
******************************************************************************/
`timescale 1 ns/ 1 ps
module clk_div_tb;
reg clk_in;
reg reset_n;
wire clk_out;
//--------- set up clocks-----------------------------
parameter ck_period = 20; // 50Mhz
always #(ck_period/2) clk_in = ~clk_in;
//--------initial signals-----------------------------
initial begin
clk_in = 1'b0;
reset_n = 1'b0;
#(10*ck_period) reset_n = 1'b1;
end
//-------module instantiation------------------------
clk_div top_inst(
.clk_in (clk_in),
.reset_n (reset_n),
.clk_out (clk_out)
);
endmodule
3. Tcl脚本文件
①gui_sim.bat，批处理文件，用于在windows cmd下运行整个modelsim仿真；
输入以下代码，保存文件为gui_sim.bat。源码如下：
vsim -do clk_sim.do
②clk_sim.do，tcl脚本文件，用于启动Modelsim仿真；
输入以下代码，保存文件为clk_sim.do。源码如下：
# Create the work library
vlib work
vmap work work
# Now compile the Verilog files one by one
vlog -work work clk_div.v
vlog -work work clk_div_tb.v
# Now run the simulation
vsim \
-voptargs=+acc \
+transport_int_delays \
+transport_path_delays \
+notimingchecks \
-t ps \
-noglitch \
-multisource_delay latest \
clk_div_tb
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
onbreak { resume }
do wave.do
run 100000ns
全文pdf《【yadog原创】Tcl+Modelsim简明操作教程》:
- 上一篇： 关于dos命令“cd”
- 下一篇： 【yadog原创】Tcl+Modelsim简明操作教程2
-
精密半导体参数测试解决方案 直播时间： 01月08日 10:00
/3 
文章评论（0条评论）
登录后参与讨论