标签: clk
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最近设计的一个板子，使用STM32F407ZG+DP83848，使用RMII接口，时钟由外部50M有源晶振提供。下载了官方的FreeRTOS+LWIP范例，遇到一个非常奇怪的问题： 1）一开始，我把Ethernet初始化代码里PA8(MCO1)配置的几行代码注释掉了，因为我不用PA8。发现网口初始化失败，死在 while(ETH_GetSoftwareResetStatus()==SET) 。网上搜了一下，很多人讨论这个问题，说是时钟的问题。于是我去测量50M时钟，发现在执行完PA7(RMII_CLK)的配置语句后，该引脚上的50M时钟电平幅度降了一半！！于是我怀疑晶振有问题，准备去换晶振！ 2）无意间，我把PA8的配置代码加上了（在配置PA7之前），见下面几行代码，发现一切正常了！我仅仅是配置了PA8作为复用而已，甚至都没有输出时钟！后来反复尝试，发现就是这几行代码，不加上就不行！！ /* Configure MCO (PA8) */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; GPIO_Init(GPIOA, GPIO_InitStructure); 这太奇怪了，PA8在我的板子上完全没有用，跟系统一点关系都没有。网上很多人遇到同样问题，解决方法还不一样，有的说在软件复位后再使能MAC的时钟就可以了，可我试了，不是这个问题，就是要配置PA8才行！！！ ------------------------------------------- 找到原因了，犯了一个很stupid的错误，就是把上面几行注释后， GPIO_InitStructure结构体相应的成员都没有赋值，因为后面的初始化代码只改变GPIO_Pin而已！
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作者余晓锜，文中用图解的方式详细说明了CLK时钟PCB走线的相关原则及对EMI的影响问题。
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Asreal-timedigitalsignalprocessing(DSP)systemsbecomemorecomplicatedwithmultiplethreadsofexecutionandfasterDSPs,softwaredevelopmentanddebuggingbecomesmorecomplicated.AnMP3playerisagoodexampleofamulti-threadedsystemthatexecutesnotonlyDSP-type(data)threadssuchasMP3decoding,samplerateconversion,andgraphicequalization,butitalsorunstypical“host/controller”(control)threadssuchasuserinterface(keypad/LCD)andaccesstostoragemedia(forexample,CompactFlash).Inthisdocumentwediscussthesoftwarebehindareal-worldMP3playerrunningstand-aloneonaTexasInstrumentsC5000EDSP.PartsofthissystemarepresentlybeingshippedinproductionMP3playersallovertheworld.ThesoftwareisbuiltupontheTexasInstrumentsDSP/BIOSofferingwithschedulerandreal-timeanalysis.Thisapplicationreportshowsastep-by-stepreal-worldsoftwareparadigmshift.WewillstartwithatypicalISR(interruptserviceroutine)systemandbuilditupinstepstoincorporatesuchconstructsasareal-timepreemptivekernelanddatapipingstructure.ThenwewillseehowDSP/BIOSreal-timeanalysis(RTA)canbeusedtoobserveanddebugtheentiresysteminrealtime.Thesedebugfeaturesincludeschedulinggraphs,loadingcalculations,andstatisticalbenchmarkinginformation.……
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Astelecomprovidersservicemorecustomersathigherspeeds,theyneedlargernetworkfacilities,whichrequirelongercablerunsbetweensystems.Interconnectsoftenusecoppercableforitspriceadvantage,butproblemsariseasdistanceanddatarateincrease.Convertingtofiber-opticbasedsystemsiscostly.Analternativeistoinstallrepeaters,whicharecost-effectiveanddonotrequirereplacingexistingequipment.Thisapplicationnotedescribesasimple,low-costrepeater.……
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Thisapplicationnoteonclock(CLK)signalqualitydescribeshowtomeasurejitterandphase-noise,includingperiodjitter,cycle-to-cyclejitter,andaccumulatedjitter.Itdescribestherelationshipbetweenperiodjitterandphase-noisespectrumandhowtoconvertthephase-noisespectrumtotheperiodjitter.……
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Peakcurrent-modecontrolispreferredbypowersupplydesignersbecauseitprovidesafirst-orderfrequencyresponsecharacteristicinthecontrol-to-outputtransferfunction.Acontrol-loopdesignprocedurebasedonthefirst-ordermodelpredictsaphasemargincloseto90degrees.Itisfound,however,thatthephasemarginobtainedinpracticeisfarlessthan90degreesdependingonchoiceofcrossoverfrequency,operatingdutycycle,andamountofslopecompensationused.Thisisduetothesamplingeffectofthecontrol-loopcurrentcomparator.Thefollowingapplicationnotedescribesacontrol-loopdesignprocedurefortheMAX1954Acurrent-modecontrollerthatconsidersthissamplingeffectandaccuratelypredictsphasemargin.ThisanalysisisnotspecifictotheMAX1954A,however,andappliestomostcurrent-modestep-downICssoldtoday.……
