标签: finfet

提到 FET ，学电子的人都比较熟悉， FET 就是 Field-Effect Transistor ，场效应管。 FET 是一种常见的三端口半导体器件，比较常见的是 JFET （结型场效应晶体管）和金属氧化物场效应管 MOSFET 。下图给出了常见的场效应管的工作示意图， 那么 FinFET 到底是什么呢？ FinFET 被称为鳍式场效应晶体管，是一种新的互补式金属氧化物半导体晶体管。该项技术的发明人是加州大学伯克利分校的胡正明教授。 FinFeT 与平面型 MOSFET 结构的主要区别在于其沟道由绝缘衬底上凸起的高而薄的鳍构成，源漏两极分别在其两端，三栅极紧贴其侧壁和顶部，用于辅助电流控制，这种鳍形结构增大了栅围绕沟道的面，加强了栅对沟道的控制，从而可以有效缓解平面器件中出现的短沟道效应，大幅改善电路控制并减少漏电流，也可以大幅缩短晶体管的栅长，也正由于该特性， FinFET 无须高掺杂沟道，因此能够有效降低杂质离子散射效应，提高沟道载流子迁移率。 FinFET 的主要特点是，沟道区域是一个被栅极包裹的鳍状半导体。沿源漏方向的鳍的长度，为沟道长度。栅极包裹的结构增强了栅的控制能力， 对沟道提供了更好的电学控制，从而降低了漏电流，抑制短沟道效应。 然而 FinFET 有很多种，不同的 FinFET 有不同的电学特性。下面根据衬底类型、沟道的方向、栅的数量、栅的结构，分别给予介绍。 SOI FinFET 和体 FinFET 。根据 FinFET 衬底， FinFET 可以分成两种。一种是 SOI FinFET ，一种是体 FinFET 。 FinFET 形成在体硅衬底上。由于制作的工艺不同，相比于 SOI 衬底，体硅衬底具有低缺陷密度，低成本的优点。此外，由于 SOI 衬底中埋氧层的热传导率较低，体硅衬底的散热性能也要优于 SOI 衬底。 Buk FinFET ， SOI FinFET 具有近似的寄生电阻、寄生电容，从而在电路水平上可以提供相似的功率性能。但是 SOI 衬底的轻鳍掺杂 FinFET ，相比于 Buk FinFET ，表现出较低的节电容，更高的迁移率和电压增益的电学性能。 FinFET 到底有多牛？ 对于场效应管，我们最常用的是 MOSFET ，全称是金属氧化物半导体场效应管： Metal Oxide Semiconductor Field Effect Transistor 。 MOSFET 在 1960 年由贝尔实验室（ Bell Lab. ）的 D. Kahng 和 Martin Atalla 首次实作成功，这种元件的操作原理和 1947 年肖克利（ William Shockley ）等人发明的双载流子结型晶体管（ Bipolar Junction Transistor,BJT ）截然不同，且因为制造成本低廉与使用面积较小、高整合度的优势，在大型集成电路（ Large-Scale Integrated Circuits,LSI ）或是超大型集成电路（ Very Large-Scale Integrated Circuits,VLSI ）的领域里，重要性远超过 BJT 。 但是 MOSFET 发明至今已有六十多年历史，随着半导体制程工艺的进步， MOSFET 的限制越来越明显。我们知道，在 MOSFET 中，栅极长度（ Gate length ）大约 10 奈米，是所有构造中最细小也最难制作的，因此我们常常以栅极长度来代表半导体工艺的进步程度，这就是所谓的工艺线宽。栅极长度会随工艺技术的进步而变小，从早期的 0.18 微米、 0.13 微米，进步到 90 奈米、 65 奈米、 45 奈米、 22 奈米，到目前最新工艺 10 奈米。当栅极长度愈小，则整个 MOSFET 就愈小，而同样含有数十亿个 MOSFET 的芯片就愈小，封装以后的集成电路就愈小，最后做出来的手机就愈小啰！。 10 奈米到底有多小呢？细菌大约 1 微米，病毒大约 100 奈米，换句话说，人类现在的工艺技术可以制作出只有病毒 1/10 （ 10 奈米）的结构，厉害吧！ 但是当栅极长度缩小到 20 奈米以下的时候，遇到了许多问题，其中最麻烦的是当闸极长度愈小，源极和漏极的距离就愈近，栅极下方的氧化物也愈薄，电子有可能偷偷溜过去产生漏电（ Leakage ）；另外一个更麻烦的问题，原本电子是否能由源极流到漏极是由闸极电压来控制的，但是栅极长度愈小，则栅极与通道之间的接触面积（图一红色虚线区域）愈小，也就是闸极对通道的影响力愈小，要如何才能保持闸极对通道的影响力（接触面积）呢？ 因此美国加州大学伯克莱分校胡正明、 Tsu-Jae King-Liu 、 Jeffrey Bokor 等三位教授发明了鳍式场效晶体管（ Fin Field Effect Transistor ， FinFET ），把原本 2D 构造的 MOSFET 改为 3D 的 FinFET ，如图二所示，因为构造很像鱼鳍 ，因此称为鳍式（ Fin ）。 由图中可以看出原本的源极和漏极拉高变成立体板状结构，让源极和漏极之间的通道变成板状，则栅极与通道之间的接触面积变大了（图二黄色的氧化物与下方接触的区域明显比图一红色虚线区域还大），这样一来即使栅极长度缩小到 20 奈米以下，仍然保留很大的接触面积，可以控制电子是否能由源极流到汲极，因此可以更妥善的控制电流，同时降低漏电和动态功率耗损，所谓动态功率耗损就是这个 FinFET 由状态 0 变 1 或由 1 变 0 时所消耗的电能，降低漏电和动态功率耗损就是可以更省电的意思啰！ FinFET 是栅极长度缩小到 20 奈米以下的关键，拥有这个技术的工艺与专利，才能确保未来在半导体市场上的竞争力。 当然场效应管也不是一成不变的， FinFET 也不会是最终的选项，其演进一直在进行中。在过去的 17 年中， CMOS 技术在制造和建筑中使用的材料方面取得了重大进展。第一个巨大飞跃是在 90 nm 技术节点引入应变工程。随后的步骤是具有 45 nm 高 k 电介质的金属栅极，以及 22 nm 节点的 FinFET 架构。 2012 年标志着第一个商用 22nm FinFET 的诞生。 FinFET 架构的后续改进提高了性能并减少了面积。 FinFET 的 3D 特性具有许多优势，例如增加鳍片高度以在相同的占位面积下获得更高的驱动电流。图 2 显示了 MOSFET 结构的演变：双栅、三栅、 pi 栅、 omega 栅和环栅。由于结构简单且易于制造，双栅极和三栅极 FinFET 很常见。尽管 GAA 器件是在 FinFET 之前提出的，但后者更适合执行生产。 未来，到底属于那种技术，让我们拭目以待，并努力向前。 关注公众号“优特美尔商城”，获取更多电子元器件知识、电路讲解、型号资料、电子资讯，欢迎留言讨论。

Technologies are impacting largely our life about how we work in office, how we socialize, how we study, how we communicate. It is inevitable to think Life without electronics in our daily life with our day to day tasks. Decade of 2010-2020 is called “Life Impact Technologies’, because each technology invented (will be invented) each year will give new way of executing life and daily operations.Infact technology is extending in to animals. Toshiba has launch world’s first laptop for dogs called “Petbook K9”.   There are two areas to watch out in 2013 : Distruptive technologies in the area of Advance Gadgets with Mobile technologies Technology advancements for 20nm below node, FinFET and multi-core architectures   We have seen that Smart gadgets like Apple, Samsung, Google phone and tablets are set to go new features in 2013. NFC (Near Field Communication) has already brought Mobile payment reality. Samsung SIII phone is roaring success with NFC. Next-gen Apple-Google-Samsung products will continue to roar. Display resolution, Camera resolution, 3D Display, 3D Gamin and TransferJet.   As per TransferJet regulatory committee “TransferJet is a new wireless technology that combines the speed of UWB (Ultra-Wide Band) with the ease of NFC (Near Field Communications). By doing so, TransferJet delivers a transfer speed of 560 Mbps available to the end user through a simple “touch."   The key concept of TransferJet is this “touch” model of user operation. This model requires only a simple touch motion from the user to make things happen. Touch is such a natural motion that people tend to “get it” very quickly. Clearly, touch is a very natural and intuitive motion. From a user standpoint, TransferJet can be thought of as a universal touch-activated interface which instantly connects a wide variety of consumer (and non-consumer) electronic products. The TransferJet technical specifications have been developed in order to realize simplicity of use based on the “touch” model.   It allows high speed data transfer between smart phone, laptop, PoC, consumer devices on touch-transfer in fraction of seconds. Toshiba, Sony Transferjet are key technologies conquer.   Advanced gadgets will be wearable gadgets coming for clothes and medical devices taking care of auto-blood pressure measurement, pulse measurement, heat-cold maintenance, music players, Toy-robot compatible advance gadgets.   Another key advances are happening in technology areas covering (1) 28nm and below technologies i.e. 20nm, 14nm, 10nm (2) FinFET and related Transistor research (3) multi core archtictures for all applications.    Ensuring designs to work on 28nm technology requires methodology, tool and library support. Hence lithography tool start up addressing needs with Lithiography optimized gate layer layout, Cut mask optimized cell architecture and gate length biasing leakage optimization.    Similarly FinFET, Suvolta’s powershrink transistor, NRAM (NanoTube RAM) has been emerging areas for enabling next decade of Electronic design.   Multicore technologies were largely driven by Microprocessor demands of quad-core CPU, Hex-core CPUs for processor giants like Intel, AMD,  however now it has been largely extended to handheld gadgets with Apple’s A4, nVidia’s Tegra, QualComm’s SnapDragon for mobile applications. High end Optical networking SoCs are now started consuming multi core architecture for networking applications for base stations , EDGE routers. Kalray has been sampling MPPA (Multi purpose processor array) with 256 core on chip. Adapteva has launched multi core architecture to meet performance and power requirements. Much of these has been start up , but with ready to launch product which will roar next generation devices for performance and speed both.   2010-2020 decade is transitioning decade for electronics industry, because gadget’s new features will drive all new chips and life style, while technology innovations will drive new innovations like FINFET, Multi-core architectures.   2013 will be another exciting year with Mobile payment, TransferJet, Advance Gadget features and technology innovations for  28nm processes, multi-core (100+) architectures. Electronics life style will be exciting journey….!     -- Nilesh Ranpura, Project Manager-ASIC, e-Infochips He has 14+ years of experience in VLSI Design Cycle, Methodology, Verification, Physical design. He has key experience in the areas of Bus Interfaces and Networking devices. Participated on multiple projects for Physical design and Multi-million gate count SoC verification architecture definition and Complete Product devlopment .

Cadence this year is nominating the FinFET, a new type of 3D transistor that promises significant power and performance advantages over the planar devices that are in common use today. FinFETs are now expected to come into common use at process nodes below 20nm, where they will allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs will thus enable new generations of high-density, high-performance and ultra-low-power systems on chip (SoCs) for future smart phones, tablets and other advanced mobile devices. FinFET technology was co-invented and described in 1999 by Chenming Hu, Tsu-Jae King-Liu, and Jeffrey Bokar at the University of California, Berkeley. Their research was a response to a request for proposal from the DARPA (Defense Advanced Research Projects Agency) for ideas on how to create ICs at 25nm and below. In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel or "fin". This solves several problems, including random variation of impurity atoms and variations in gate length. This approach also provides much more control over electrical current compared to planar or flat transistors. As a result, FinFETs both improve performance and reduce power consumption. Furthermore, they were proven to be commercially manufacturable in the spring of 2011 by Intel at 22nm, and most recently by IBM working with ARM and Cadence at 14nm. Because the FinFET channel is surrounded on three sides by the gate, and gates turn on and off much faster than with planar transistors, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. Designers can add multiple fins to provide more current. While the last several generations of technology nodes used 1 volt power supplies, FinFET technology could allow designers to go to 0.8V or 0.6V, which helps to reduce dynamic power. An important feature of FinFET technology is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling is not limited by oxide thickness. This is good aspect of the technology because current process lithography defines the FET characteristics at each new process node. It only takes one extra mask to create the silicon fin, which helps manage costs. The FinFET manufacturing process is also compatible with contemporary advanced CMOS manufacturing and production techniques. After the fin is constructed, the rest of the processing is essentially planar because the fin height is only about 30nm for a fin that's 20nm thick.     Like any new semiconductor technology, FinFETs will rely on an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration and RD investment by EDA vendors, IP providers, foundries, and semiconductor companies is crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs at 14nm and beyond. - Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization, Cadence Design Systems, Inc.    

Cadence this year is nominating the FinFET, a new type of 3D transistor that promises significant power and performance advantages over the planar devices that are in common use today. FinFETs are now expected to come into common use at process nodes below 20nm, where they will allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs will thus enable new generations of high-density, high-performance and ultra-low-power systems on chip (SoCs) for future smart phones, tablets and other advanced mobile devices. FinFET technology was co-invented and described in 1999 by Chenming Hu, Tsu-Jae King-Liu, and Jeffrey Bokar at the University of California, Berkeley. Their research was a response to a request for proposal from the DARPA (Defense Advanced Research Projects Agency) for ideas on how to create ICs at 25nm and below. In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel or "fin". This solves several problems, including random variation of impurity atoms and variations in gate length. This approach also provides much more control over electrical current compared to planar or flat transistors. As a result, FinFETs both improve performance and reduce power consumption. Furthermore, they were proven to be commercially manufacturable in the spring of 2011 by Intel at 22nm, and most recently by IBM working with ARM and Cadence at 14nm. Because the FinFET channel is surrounded on three sides by the gate, and gates turn on and off much faster than with planar transistors, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. Designers can add multiple fins to provide more current. While the last several generations of technology nodes used 1 volt power supplies, FinFET technology could allow designers to go to 0.8V or 0.6V, which helps to reduce dynamic power. An important feature of FinFET technology is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling is not limited by oxide thickness. This is good aspect of the technology because current process lithography defines the FET characteristics at each new process node. It only takes one extra mask to create the silicon fin, which helps manage costs. The FinFET manufacturing process is also compatible with contemporary advanced CMOS manufacturing and production techniques. After the fin is constructed, the rest of the processing is essentially planar because the fin height is only about 30nm for a fin that's 20nm thick.   Like any new semiconductor technology, FinFETs will rely on an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration and RD investment by EDA vendors, IP providers, foundries, and semiconductor companies is crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs at 14nm and beyond. - Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization, Cadence Design Systems, Inc.  

Despite persistent economic doom and gloom, electronic design automation (EDA) vendors are poised for a strong 2013 as the semiconductor industry prepares to transition to three-dimensional FinFET transistors while continuing to push the envelope with scaling to smaller process geometries, according to Aart de Geus, chairman and CEO of Synopsys Inc. Synopsys—the largest EDA vendor—reported another strong quarter and fiscal year last December—posting sales that exceeded analysts' expectations. The report followed a similar strong performance by Mentor Graphics Corp.—another of EDA's "big three"—last week. "I think EDA in general and Synopsys in particular are very well positioned for 2013," de Geus said in an interview Wednesday following the quarterly report. De Geus believes his company and EDA as a whole are poised to cash in by helping chip makers undertake enormous technical challenges amid fierce competition. Intel Corp. has already put its version of FinFET transistors—which Intel calls tri-gate transistors—into production. TSMC, Samsung, UMC and Globalfoundries all want to put FinFET technology into production in 2014. Foundry customers that want to get in on the ground floor of this technology must act quickly. "The number of technical challenges is substantially higher than in the past," de Geus said. "We do see that customers need a lot of support to build the next generation of chips." That need for support, of course, is music to the years of EDA vendors, who make their living alleviating customers' pain points. EDA—which in recent years has been perhaps unfairly labelled a low-growth industry with limited potential—has genuine opportunity in the years ahead as chip vendors tangle with massive new technical hurdles while fighting each other for every scrap of market share. "The pressure is really high for customers to come up with the next chip sets to win," de Geus said. Synopsys reported sales of $454.2 million for its fiscal fourth quarter, up 2 per cent sequentially and16 per cent year-to-year. The company reported a GAAP net income of $29.1 million, or 19 cents per share, down from a GAAP net income of $75.7 million in the previous quarter and $39.9 million in the year-ago quarter. On a non-GAAP basis, excluding charges, Synopsys reported a net income for the quarter of $72.4 million, or 47 cents per share, down from $82.3 million in the previous quarter and up from $65.3 million in the year ago quarter. For the fiscal year, Synopsys reported sales of $1.756 billion, up 14 per cent from fiscal 2011. The company's GAAP net income for the year was $182.4 million, or $1.21 per share, down 18 per cent from fiscal 2011. Synopsys forecast sales for the fiscal first quarter to be between $468 million and $478 million, with GAAP earnings per share of 30 to 35 cents. For fiscal 2013, Synopsys said it expects sales to increase to between $1.955 billion and $1.975 billion.