tag 标签: 小技

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  • 所需E币: 5
    时间: 2020-1-10 10:14
    大小: 28.5KB
    上传者: quw431979_163.com
    Allegro小技巧如何察看已加测点及百分率?命令route\Tstprep\TestpinCheck出现Testcheck窗口,选择TestPointDistandPadstackCheck即可出现结果。1.拉线时不能自动切换到所在层,这是为何?命令Setup\UserPreferences将第一项acon_route_on_active_subclass的钩去掉即可。2.Routekeepin&packagekeepin小板子20mil,大板子40mil.做负片时gnd的antietch宽度为小板子20mil,大板子40mil.VCC的antietch的宽度为小板子40mil,大板子80mil4.蛇形线的走法先将线弯曲为蛇形,再通过slide命令调整。调整时右边control窗口的options中的max45len调为4.0。bubble为off.将线调为蛇形即可。线的间距至少为线宽的2倍。3.替换Via的方法将新的via文档拷到当前目录下,命令Tools\Padstack\Replace,按窗口命令操作即可。4.设定Constraintsarea步骤Setup\Constraints点Areas框中的Add.右边Control框下Options中的ActiveClassandSubclass分别选BARDGEOMETRY和CONSTRAINTS_AREA.选好后在板上划出设定的区域。划好后点击Cnstraints……
  • 所需E币: 5
    时间: 2020-1-13 16:07
    大小: 150.55KB
    上传者: 238112554_qq
    ADS小技巧10HelpfulHintsforusingtheHPAdvancedDesignSystemHINTSCONTENTSLearningto“Drive”UsingtheKeyboard..............................................................................3UsingTemplatesorCopyingExamplesforMoreEfcientSimulationSet-upandDataDisplay...........................................................................................................................4SavingMouseClickswhenOpeningProjects....................................................................5RenamingPortsonSchematicsbeforeGeneratingSubcircuits.......................................6EnablingEasyDisplayofData..............................................................................................7EfcientlyCalculateCircuitEnvelopeSimulationData……
  • 所需E币: 3
    时间: 2020-1-15 09:47
    大小: 190.4KB
    上传者: wsu_w_hotmail.com
    FPGA设计小技巧(good)……