tag 标签: phaselockedloop

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  • 所需E币: 4
    时间: 2020-1-14 15:36
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    PhaseLockedLoop_2006--DESIGNPHASELOCKEDLOOPDESIGNbyKristenElserougi,RanilFernando,LucaWeiSENIORDESIGNPROJECTREPORTSubmittedinpartialfulfillmentoftherequirementsforthedegreeofBachelorofScienceinElectricalEngineeringSchoolofEngineeringSantaClaraUniversitySantaClara,CaliforniaJune20,2006AbstractOurteamchosetodoacompletemixedsignalICdesignprocess.Withthispurpose,wedecidedtodesignaPhaseLockedLoop(PLL)becausethedesignprocesswouldincorporatetopicsfromdigital,analog,ICdesign,andcontrolsystemstheory.Thisrangeoftopicsisanadequatewaytoincorporatetheprimaryelectricalengineeringtheoriesintooneproject.APLLisaclosedloopfrequencysystemthatlocksthephaseofanoutputsignaltoaninputreferencesignal.Theterm“loc……