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2011-10-5 17:23
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The beauty of the nameless sequence is that whenever the number of wires double we only have to add one new test pattern. That is, 8 wires require 4 test patterns, 16 wires require 5 test patterns, 32 wires require 6 test patterns, and so on. Thus, as the number of wires increase, so does the efficiency of the "nameless" sequence in comparison to the walking ones sequence. Note that if you're using the "nameless" sequence and the number of wires is not equal to a power of two (2, 4, 8, 16, 32, 64, ...), then you can add some imaginary wires to create the sequence and discard them at the end. For example, if you have 5, 6, or 7 wires, you would add enough pseudo-wires to bring the total number of wires up to 8, write the test sequence based on 8 wires, and then drop the pseudo wires. The "nameless" sequence unmasked! After I had first mentioned my "nameless" sequence in an article in EDN magazine many years ago, I received a jolly pleasant letter from Mr. Norman Megill, Vice President of Engineering at Production Services Corporation, Belmont, MA. Mr. Megill pointed out that my "nameless" sequence should more properly be referred to as the Modified Counting Sequence Algorithm as per a 1989 IEEE paper: N. Jarwala and C.W. Yau, "A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects," Proceedings, IEEE International Test Conference, 1989, pp. 63-70 Mr. Megill went on to note that, to the best of his knowledge, this algorithm was first documented by himself in a 1979 paper: N.D. Megill, "Techniques for Reducing Pattern Counts for Functional Testing," Digest of Papers, IEEE Test Conference 1979, pp. 90-94 In fact my discussions on the nameless sequence prompted a slew of emails from readers who had independently come up with the same thing. Furthermore, several readers noted a trick they used to generate a variation on the nameless sequence, which simply involves writing down a standard binary count sequence, commencing at 1, proceeding up to the number of wires you wish to test, and then "rotating" the results. For example, assuming that we wish to test 10 wires called a through j for stuck-ats, bridges, and open faults, we would commence by writing the binary values for 1 to 10 as illustrated in Figure 3(a). Figure 3: Generating a variation of the nameless sequence. Once we've generated the binary count, we conceptually "rotate" the table 90 degrees clockwise (or anti-clockwise if you are so-inclined) to create the final test sequence as illustrated in Figure 3(b). This scheme has an advantage over my nameless sequence in that it results in one less test for any number of wires except 2 n (I tell you, I learn something new every day). Actually testing the device Using the "nameless" sequence (or similar) to generate addresses, we would first write corresponding "nameless-sequence-based" data values into each "nameless" location and then read these values back again. This would ensure that we had access to the device and that there were no short, open, or bridging faults on the address or data busses. The next step would be to write functional tests that verify the internals of each memory device, but these techniques are a tad more complex and will therefore be left as topics for future columns. And the answer is... And so, returning to my original tale of woe, how could it be that my tests passed when there wasn't even any memory in the cabinet? Arrggghhh! It was all due to parasitic capacitances on the data and address busses. Whatever 010101... (or similar) value that I wrote to the bus persisted long enough for me to read it back again. I cannot tell you how silly I felt when I discovered my mistake, but that's how we learn... the real trick is to not make the same mistake more than once (grin).