标签: verilog实现的4.5倍分频

代码如下：   module div_4_5(clk,rst,clkout); input clk,rst; output clkout;   reg cnt_p; reg cnt_n;   reg clk_p,clk_n;   assign clkout=clk_p || clk_n;   always @ (posedge clk or negedge rst) begin  if(!rst)   cnt_p=4'd0;  else if(cnt_p==4'd8)   cnt_p=4'd0;  else   cnt_p=cnt_p+4'd1; end   always @ (posedge clk or negedge rst) begin  if(!rst)   clk_p=1'd0;  else if(cnt_p==4'd1 || cnt_p==4'd2 || cnt_p==4'd6 || cnt_p==4'd7)   clk_p=1'd1;  else   clk_p=1'd0; end   always @ (negedge clk or negedge rst) begin  if(!rst)   cnt_n=4'd0;  else if(cnt_p==3'd1)   cnt_n=4'd1;  else if(cnt_n==4'd8)   cnt_n=4'd0;  else if(cnt_n==4'd0)   cnt_n=4'd0;  else   cnt_n=cnt_n+4'd1; end   always @ (negedge clk or negedge rst) begin  if(!rst)   clk_n=1'd0;  else if(cnt_n==4'd1 || cnt_n==4'd2 || cnt_n==4'd6 || cnt_n==4'd5)   clk_n=1'd1;  else   clk_n=1'd0; end   endmodule 仿真结果：