tag 标签: finfet

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  • 热度 1
    2013-4-13 04:14
    2828 次阅读|
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    Technologies are impacting largely our life about how we work in office, how we socialize, how we study, how we communicate. It is inevitable to think Life without electronics in our daily life with our day to day tasks. Decade of 2010-2020 is called “Life Impact Technologies’, because each technology invented (will be invented) each year will give new way of executing life and daily operations.Infact technology is extending in to animals. Toshiba has launch world’s first laptop for dogs called “Petbook K9”.   There are two areas to watch out in 2013 : Distruptive technologies in the area of Advance Gadgets with Mobile technologies Technology advancements for 20nm below node, FinFET and multi-core architectures   We have seen that Smart gadgets like Apple, Samsung, Google phone and tablets are set to go new features in 2013. NFC (Near Field Communication) has already brought Mobile payment reality. Samsung SIII phone is roaring success with NFC. Next-gen Apple-Google-Samsung products will continue to roar. Display resolution, Camera resolution, 3D Display, 3D Gamin and TransferJet.   As per TransferJet regulatory committee “TransferJet is a new wireless technology that combines the speed of UWB (Ultra-Wide Band) with the ease of NFC (Near Field Communications). By doing so, TransferJet delivers a transfer speed of 560 Mbps available to the end user through a simple “touch."   The key concept of TransferJet is this “touch” model of user operation. This model requires only a simple touch motion from the user to make things happen. Touch is such a natural motion that people tend to “get it” very quickly. Clearly, touch is a very natural and intuitive motion. From a user standpoint, TransferJet can be thought of as a universal touch-activated interface which instantly connects a wide variety of consumer (and non-consumer) electronic products. The TransferJet technical specifications have been developed in order to realize simplicity of use based on the “touch” model.   It allows high speed data transfer between smart phone, laptop, PoC, consumer devices on touch-transfer in fraction of seconds. Toshiba, Sony Transferjet are key technologies conquer.   Advanced gadgets will be wearable gadgets coming for clothes and medical devices taking care of auto-blood pressure measurement, pulse measurement, heat-cold maintenance, music players, Toy-robot compatible advance gadgets.   Another key advances are happening in technology areas covering (1) 28nm and below technologies i.e. 20nm, 14nm, 10nm (2) FinFET and related Transistor research (3) multi core archtictures for all applications.    Ensuring designs to work on 28nm technology requires methodology, tool and library support. Hence lithography tool start up addressing needs with Lithiography optimized gate layer layout, Cut mask optimized cell architecture and gate length biasing leakage optimization.    Similarly FinFET, Suvolta’s powershrink transistor, NRAM (NanoTube RAM) has been emerging areas for enabling next decade of Electronic design.   Multicore technologies were largely driven by Microprocessor demands of quad-core CPU, Hex-core CPUs for processor giants like Intel, AMD,  however now it has been largely extended to handheld gadgets with Apple’s A4, nVidia’s Tegra, QualComm’s SnapDragon for mobile applications. High end Optical networking SoCs are now started consuming multi core architecture for networking applications for base stations , EDGE routers. Kalray has been sampling MPPA (Multi purpose processor array) with 256 core on chip. Adapteva has launched multi core architecture to meet performance and power requirements. Much of these has been start up , but with ready to launch product which will roar next generation devices for performance and speed both.   2010-2020 decade is transitioning decade for electronics industry, because gadget’s new features will drive all new chips and life style, while technology innovations will drive new innovations like FINFET, Multi-core architectures.   2013 will be another exciting year with Mobile payment, TransferJet, Advance Gadget features and technology innovations for  28nm processes, multi-core (100+) architectures. Electronics life style will be exciting journey….!     -- Nilesh Ranpura, Project Manager-ASIC, e-Infochips He has 14+ years of experience in VLSI Design Cycle, Methodology, Verification, Physical design. He has key experience in the areas of Bus Interfaces and Networking devices. Participated on multiple projects for Physical design and Multi-million gate count SoC verification architecture definition and Complete Product devlopment .
  • 2013-1-9 12:13
    1510 次阅读|
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    Cadence this year is nominating the FinFET, a new type of 3D transistor that promises significant power and performance advantages over the planar devices that are in common use today. FinFETs are now expected to come into common use at process nodes below 20nm, where they will allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs will thus enable new generations of high-density, high-performance and ultra-low-power systems on chip (SoCs) for future smart phones, tablets and other advanced mobile devices. FinFET technology was co-invented and described in 1999 by Chenming Hu, Tsu-Jae King-Liu, and Jeffrey Bokar at the University of California, Berkeley. Their research was a response to a request for proposal from the DARPA (Defense Advanced Research Projects Agency) for ideas on how to create ICs at 25nm and below. In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel or "fin". This solves several problems, including random variation of impurity atoms and variations in gate length. This approach also provides much more control over electrical current compared to planar or flat transistors. As a result, FinFETs both improve performance and reduce power consumption. Furthermore, they were proven to be commercially manufacturable in the spring of 2011 by Intel at 22nm, and most recently by IBM working with ARM and Cadence at 14nm. Because the FinFET channel is surrounded on three sides by the gate, and gates turn on and off much faster than with planar transistors, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. Designers can add multiple fins to provide more current. While the last several generations of technology nodes used 1 volt power supplies, FinFET technology could allow designers to go to 0.8V or 0.6V, which helps to reduce dynamic power. An important feature of FinFET technology is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling is not limited by oxide thickness. This is good aspect of the technology because current process lithography defines the FET characteristics at each new process node. It only takes one extra mask to create the silicon fin, which helps manage costs. The FinFET manufacturing process is also compatible with contemporary advanced CMOS manufacturing and production techniques. After the fin is constructed, the rest of the processing is essentially planar because the fin height is only about 30nm for a fin that's 20nm thick.     Like any new semiconductor technology, FinFETs will rely on an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration and RD investment by EDA vendors, IP providers, foundries, and semiconductor companies is crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs at 14nm and beyond. - Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization, Cadence Design Systems, Inc.    
  • 2013-1-9 10:58
    2133 次阅读|
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    Cadence this year is nominating the FinFET, a new type of 3D transistor that promises significant power and performance advantages over the planar devices that are in common use today. FinFETs are now expected to come into common use at process nodes below 20nm, where they will allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs will thus enable new generations of high-density, high-performance and ultra-low-power systems on chip (SoCs) for future smart phones, tablets and other advanced mobile devices. FinFET technology was co-invented and described in 1999 by Chenming Hu, Tsu-Jae King-Liu, and Jeffrey Bokar at the University of California, Berkeley. Their research was a response to a request for proposal from the DARPA (Defense Advanced Research Projects Agency) for ideas on how to create ICs at 25nm and below. In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel or "fin". This solves several problems, including random variation of impurity atoms and variations in gate length. This approach also provides much more control over electrical current compared to planar or flat transistors. As a result, FinFETs both improve performance and reduce power consumption. Furthermore, they were proven to be commercially manufacturable in the spring of 2011 by Intel at 22nm, and most recently by IBM working with ARM and Cadence at 14nm. Because the FinFET channel is surrounded on three sides by the gate, and gates turn on and off much faster than with planar transistors, leakage is substantially reduced. Vdd and dynamic power are significantly lower as well. Designers can add multiple fins to provide more current. While the last several generations of technology nodes used 1 volt power supplies, FinFET technology could allow designers to go to 0.8V or 0.6V, which helps to reduce dynamic power. An important feature of FinFET technology is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling is not limited by oxide thickness. This is good aspect of the technology because current process lithography defines the FET characteristics at each new process node. It only takes one extra mask to create the silicon fin, which helps manage costs. The FinFET manufacturing process is also compatible with contemporary advanced CMOS manufacturing and production techniques. After the fin is constructed, the rest of the processing is essentially planar because the fin height is only about 30nm for a fin that's 20nm thick.   Like any new semiconductor technology, FinFETs will rely on an ecosystem that includes EDA tools, process design kits (PDKs), physical IP, and silicon-proven manufacturing processes. Early collaboration and RD investment by EDA vendors, IP providers, foundries, and semiconductor companies is crucial. In the coming year Cadence will continue actively working with its partners on EDA support, SPICE models, and test chips for next generation SoCs at 14nm and beyond. - Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization, Cadence Design Systems, Inc.  
  • 热度 1
    2012-12-11 19:52
    1268 次阅读|
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    Despite persistent economic doom and gloom, electronic design automation (EDA) vendors are poised for a strong 2013 as the semiconductor industry prepares to transition to three-dimensional FinFET transistors while continuing to push the envelope with scaling to smaller process geometries, according to Aart de Geus, chairman and CEO of Synopsys Inc. Synopsys—the largest EDA vendor—reported another strong quarter and fiscal year last December—posting sales that exceeded analysts' expectations. The report followed a similar strong performance by Mentor Graphics Corp.—another of EDA's "big three"—last week. "I think EDA in general and Synopsys in particular are very well positioned for 2013," de Geus said in an interview Wednesday following the quarterly report. De Geus believes his company and EDA as a whole are poised to cash in by helping chip makers undertake enormous technical challenges amid fierce competition. Intel Corp. has already put its version of FinFET transistors—which Intel calls tri-gate transistors—into production. TSMC, Samsung, UMC and Globalfoundries all want to put FinFET technology into production in 2014. Foundry customers that want to get in on the ground floor of this technology must act quickly. "The number of technical challenges is substantially higher than in the past," de Geus said. "We do see that customers need a lot of support to build the next generation of chips." That need for support, of course, is music to the years of EDA vendors, who make their living alleviating customers' pain points. EDA—which in recent years has been perhaps unfairly labelled a low-growth industry with limited potential—has genuine opportunity in the years ahead as chip vendors tangle with massive new technical hurdles while fighting each other for every scrap of market share. "The pressure is really high for customers to come up with the next chip sets to win," de Geus said. Synopsys reported sales of $454.2 million for its fiscal fourth quarter, up 2 per cent sequentially and16 per cent year-to-year. The company reported a GAAP net income of $29.1 million, or 19 cents per share, down from a GAAP net income of $75.7 million in the previous quarter and $39.9 million in the year-ago quarter. On a non-GAAP basis, excluding charges, Synopsys reported a net income for the quarter of $72.4 million, or 47 cents per share, down from $82.3 million in the previous quarter and up from $65.3 million in the year ago quarter. For the fiscal year, Synopsys reported sales of $1.756 billion, up 14 per cent from fiscal 2011. The company's GAAP net income for the year was $182.4 million, or $1.21 per share, down 18 per cent from fiscal 2011. Synopsys forecast sales for the fiscal first quarter to be between $468 million and $478 million, with GAAP earnings per share of 30 to 35 cents. For fiscal 2013, Synopsys said it expects sales to increase to between $1.955 billion and $1.975 billion.  
  • 热度 1
    2011-5-31 13:22
    1320 次阅读|
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    The delicate balance preserved over the last decade or so among circuit designers, processor architects, and embedded system hardware and software developers has been disturbed. The cause -- Intel's shift to the new 22nm CMOS process technology in its Atom CPU road map.   What is upsetting the balance and may force a rethink of every aspect of embedded systems design is Intel's shift away from a well understood planar structure to a vertical 3D FinFET. The company claims that going vertical allows significantly higher performance at lower power than most planar techniques. If Intel is successful, it will be hard for ARM and its licensees and other CPU architectures to avoid making the jump as well.   In the past, as semiconductor manufacturers went to smaller nanometer geometries with traditional planar CMOS designs, developers at all levels—circuit and logic design, processor architecture, and software development—have been able to adjust.   Working within the planar CMOS structure, they found ways to not only take advantage of the improvements in density, performance and power, but also deal with the problems of leakage, noise, reliability, EMI and ESD that nanometer scaling caused.   Several questions occur to me. If such a change is necessary, are the tough issues relating to reliability and performance with vertical FinFET structures well understood? And will many of the techniques developers have developed in planar CMOS designs still apply? Or will everything have to be rethought? Is such a vertical move at the process level necessary across all embedded CPU designs? Or is it something forced on Intel by the nature of its X86 architecture?   I would like to hear from you, pro and con, in the form of blogs and opinion commentary and as design articles about how you are dealing with the changes.
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