标签: Pearl

A week or so ago, my chum Shakeel from Blue Pearl Software and I were discussing the plethora of interfaces available to designers today and the challenges that arise when FPGA and ASIC designers implement designs with many clocks.   Out of all the challenges, perhaps the most challenging is metastability. At its most basic level, this is what happens within a register when data changes too soon before or after the active clock edge -- that is, when setup or hold times are violated.   When data is transferred between two registers with asynchronous clocks, metastability will happen. It's not a question of if it will happen; the only question is when. The thing to note is that there is no way to prevent this. All you can do is minimize its impact by placing the two clocks in different clock domains and using a synchronization technique at the crossing point, hence the term clock domain crossing.   By some strange quirk of fate, Blue Pearl has an ACE up its sleeve that solves this problem for designers in a very unique way. The Advanced Clock Environment (ACE) provides a graphical representation summarizing data paths between clocks, and it can make recommendations for grouping of clocks into domains.   With ACE, designers can identify clocks to understand how they interact with synchronizers in the design. This allows users to identify improper synchronizers or domain groupings quickly. ACE will locate errors in clock domain groupings and/or recommend appropriate domain groupings for a circuit that is synchronized.   More information can be found by clicking here . Of particular interest is that Blue Pearl has just started a campaign that lets engineers try out ACE for free .

Several days ago, my chum Shakeel from Blue Pearl Software and I were discussing the plethora of interfaces available to designers today and the challenges that arise when FPGA and ASIC designers implement designs with many clocks.   Out of all the challenges, perhaps the most challenging is metastability. At its most basic level, this is what happens within a register when data changes too soon before or after the active clock edge -- that is, when setup or hold times are violated.   When data is transferred between two registers with asynchronous clocks, metastability will happen. It's not a question of if it will happen; the only question is when. The thing to note is that there is no way to prevent this. All you can do is minimize its impact by placing the two clocks in different clock domains and using a synchronization technique at the crossing point, hence the term clock domain crossing.   By some strange quirk of fate, Blue Pearl has an ACE up its sleeve that solves this problem for designers in a very unique way. The Advanced Clock Environment (ACE) provides a graphical representation summarizing data paths between clocks, and it can make recommendations for grouping of clocks into domains.   With ACE, designers can identify clocks to understand how they interact with synchronizers in the design. This allows users to identify improper synchronizers or domain groupings quickly. ACE will locate errors in clock domain groupings and/or recommend appropriate domain groupings for a circuit that is synchronized.   More information can be found by clicking here . Of particular interest is that Blue Pearl has just started a campaign that lets engineers try out ACE for free .