标签: links

Less than a decade ago, parallel buses were king and they were the primary means of moving information between systems, within systems and boards, and between components on a printed circuit board in a design. Now, high speed serial interconnects are dominant in almost every embedded systems design, from consumer and mobile devices to the high end routers and switches that power the wired Internet backbone. The range of designs that an embedded systems developer must be sure have reliable and high quality signal integrity over such interconnections range from car rear-view camera systems, where the data rate is usually less than 1Gbit/s to high-bandwidth Internet optical routers, where data rates are 10Gbps or more. Fortunately – or unfortunately depending on how you look at the problem—there are a number of different serial interconnect topologies and standard to help you, including SuperSpeed USB (Universal Serial Bus) 3.0, PCIe (Peripheral Component Interconnect Express), XAUI (10-Gbit attachment-unit interface), InfiniBand, RapidIO, and SATA (serial advanced-technology attachment) transmit data and clock signals using differential signals. And common to them all is the ubiquitous and ever useful serialiser/deserialiser (SERDES) interface that converts data signals back and forth between serial and parallel form. A commonality amongst such protocols is that the data transmitted embeds the clock, and the receiving system often uses 8b/10b encoding to provide a means of reliable clock extraction. Multilane implementations of these technologies bring further complexities. Four, eight, or more serial lanes carry signal components from transmitters to receivers, all with the goal of higher data throughput. In such topologies it can become a considerable challenge to hunt down and find even such mundane problems as a clock that intermittently outputs an incorrect duty cycle or a rise time that occasionally fails specifications. Adding to the challenge of ensuring signal integrity is that many of these complex high-speed serial buses use a variety of CDR (clock-data-recovery) techniques for data transmission or specilazed 8b/10b encoding schemes. Adding to the complexity of the problem is the trend towards multi-lane serial configurations. Facing such ongoing challenges in such designs requires that embedded developers continually educate themselves in all of the techniques and methodologies available. A good first step is to rely on web site resources where we are constantly adding to a knowledge base that has taken us a decade or more to create on the various serial design techniques available. These resources come in the form of design articles, technical papers and webinars, complemented with a range of relevant news and product stories. Because high speed serial interconnects will be with us for a long time, our goal is to continue to provide the most relevant design information available. For that we require your participation as well, in the form of blogs and design articles on serial interconnect design that you submit as well as your suggestions about the kind of content that would be most useful to you. I look forward to hearing from you.