标签: ad_7842

  module ad_7842_1(CLK,RESET,BUSY,ad_data,CLK1MHZ,CS,WR,RD,A0,A1,num); input CLK; input RESET; input BUSY; input ad_data; output CLK1MHZ; output CS; output WR; output RD; output A0; output A1; output num; wire CLK1MHZ; reg CS; reg WR; reg RD; wire A1; wire A0; wire ad_data; reg num; reg   start; reg        clk1us; reg   count; assign A0=1'b0; assign A1=1'b0; assign CLK1MHZ=clk1us; always @(posedge CLK or negedge RESET) begin   if(RESET==1'b0) begin   count=0; end else begin if (count==49) begin count=0; clk1us=~clk1us; end else begin count=count+1; end end end always @(posedge clk1us or negedge RESET) begin if(RESET==1'b0)   begin   start=4'd0;   CS=1'b1;   WR=1'b1;   RD=1'b1;   num =12'b0; end else begin case (start) 4'd0: begin CS=1'b1; WR=1'b1; RD=1'b1; start=4'd1; end 4'd1: begin CS=1'b0; WR=1'b1; RD=1'b1; start=4'd2; end 4'd2: begin CS=1'b0; WR=1'b0; RD=1'b1; start=4'd3; end 4'd3: begin CS=1'b1; WR=1'b1; RD=1'b1; start=4'd4; end 4'd4: begin if(BUSY==1'b0) begin start=4'd5; end else begin start=4'd0; end end 4'd5: begin if(BUSY==1'b0) begin start=4'd6; end else begin start=4'd0; end end 4'd6: begin CS=1'b0; RD=1'b0; num =ad_data ; start=4'd7; end 4'd7: begin start=4'd0;  end default : begin start=4'd0;  end endcase end end endmodule 群友的，留下来，备用