标签: netlist

在Capture CIS中完成原理图编辑修改后，导出网表时，出现了以下错误：   #192 ERROR(ORCAP-36004): Conflicting values of part name found on different sections of "U1". Conflicting values: EP4CE75F23C8N_FG484_1D0_12X12MM_(S1+S2+S3+S4)_EP4CE75F23C8N EP4CE75F23C8N_4_FG484_1D0_12X12MM_(S1+S2+S3+S4)_EP4CE75F23C8N Property values of "Device","PCB FootPrint", "Class" and "Value" should be identical  on all sections of the part. #193 ERROR(ORCAP-36018): Aborting Netlisting... Please correct the above errors and retry.   问题出现情况： 在CIS中，我要对其中一个元件的原理图封装进行了一点修改（更改芯片的一个引脚名），该FPGA元件分为4个Part，右键点击需要更改引脚的Part4，选择Edit Part。 完成编辑后Close，弹出窗口选择Update Current；原理图保存生成网表时，却出现了以上的错误。   问题解决： 1、右键点击刚修改过的FPGA元件的Part4，点击Edit Part，进入元件编辑界面，跳转到该元件的Part4； 2、然后选择Options - Package Properties，如下图所示：   3、弹出如下窗口；   注意到该Part Name变成了EP4CE75F23C8N _4 ，多了个尾缀 _4 ，将该尾缀去掉，保存并更新元件； 然后再导出网表，以上出现的错误问题解决。   小结： 出现以上问题的根源是：在编辑完元件后，软件自动将该Part部分的Name添加了尾缀_4，导致该Part部分与其它三个Part名称不同，但是它们其它的属性（如：Device、PCB FootPrint、Class、Value等）又都是相同的，造成冲突。 按照以上方法更改相关Part名称后，即可解决该问题。 以后在原理图中在线修改元件的原理图封装时（尤其一个元件被划分为多部分时），尤其需注意避免该问题的出现。  

Editor's Note: This "How it used to be" piece was emailed to me by a reader named Glen. I'm still trying to persuade him to send me a pair of "Then" and "Now" photos showing him as a young engineer and as the seasoned professional of today. In the mid '80s my employer was using CAD in the drafting department for PCB layout, but the engineers still drew their schematics with a drafting table, D-size mylar, plastic symbol stencil, HB pencil, and – of course – a pencil rebooter (aka an electric pencil sharpener). The component delete function was performed with an electric rotary eraser. The move to CAE was filled with many highly-frustrating learning curve errors. Workstations that crashed and ate the unsaved schematic when one was too fast on the mouse (the 'fix' was to shut off the cursor to slow down the engineer). Components with hidden power pins that were supposed to automatically connect to power and didn't (or did, but they connected to the wrong voltage). Thousands of text warnings and errors to wade through to find one that was meaningful. Schematic sets that took three hours to print (but could at least be photocopied easily). Compiles that had to run on the same workstation that the schematic was drawn on. I could go on, but suffice it to say the early days of CAE were not easy, and all of these "features" caused a lot of trouble to engineers who were more concerned with the actual electronic design than fighting with cranky system issues. Of course, management thought CAE was a wonderful time saver. However, some things that early CAE did do well after all the compiling bugs were eventually fixed were the back annotation (re-naming reference designators to match physical PCB location), creating the BOM (electronic parts only, mechanical parts were still added by hand), and netlist generation. Especially the netlist generation. Since the drafting folks used CAD, there HAD to be a netlist – they did not look at the schematics anymore. This is how we created the netlist before CAE: First we asked the drafting department to make a set of blueprints of our D-size mylar film drawings. Then we commandeered a meeting room for several days and hung the paper schematics on the walls all around the meeting room. A bunch of engineers would walk around with yellow highlighters and trace out every single net on every sheet, identified by name. One person would sit at a table and write down (yes, by hand) all component and pin reference numbers as the engineers called them out. At the end of several days the final check was to make sure every connection on the schematics had been yellowed, and hope the transcriber had not made any errors. Checking this would have taken almost as long as the original activity. Then after the drafting department had finished the layout we had to perform back annotation. Manufacturing insisted that reference designations had to be in a sequential order on the PCB instead of randomly assigned while drawing the schematics. The drafting department would return a hand-written from/to list of all the new component reference designations which we then had to manually copy to the original schematic mylars. In one case, a colleague went to fetch the list and the draftsperson fished the only existing list out of his wastebasket ( "What the heck do you need this for?" ). The back annotation included any gate swaps that the draftsperson did to facilitate trace routing. Usually was not a problem since it normally did not matter which gate in a package was used. But this is not true for packages in which banks of buffers are tristated through control pins. Fortunately we caught this while transferring the gate swaps to the schematic. ( "But you told me I could swap gates!" ) After final layout we had drafting plot a set of Gerber films for inspection. Ever tried viewing black and clear Gerber plots through each other on a light table? Engineers did not have access to the CAD equipment to view multi-multiple layers in separate colours. Yes, early CAE had its good points as well as bad points. A humourous incident after we went to CAE was that one of the management people told the office admins to stop ordering 0.5 mm pencil leads since the engineers were now using CAE. We quickly got that situation rectified.