标签: 静态数码管

静态数码管/*----------------------------------------------------------Engineer:zhrscut--CreateDate:--ModuleName:--ToolVersions:Quartus_II9.1--欢迎加入EEPW，FPGA开发板DIY活动--------------------------------------------------------*//*----------------------------------------------------------Engineer:zhrscut--CreateDate:--ModuleName:--ToolVersions:Quartus_II9.1---EEPWFPGA°DIY--------------------------------------------------------*/modulestatic_segled(clk,rst_n,sel,data);inputclk;inputrst_n;output[7:0]sel;output[7:0]data;reg[7:0]data;wire[7:0]sel;reg[3:0]num;reg[28:0]cnt;assignsel=8'b0000_0000;always@(posedgeclkornegedgerst_n)if(!rst_n)cntelsecntalways@(cnt[25])beginnum={cnt[28:25]};end//-……