标签: reset

依稀记得前不久总结过一篇有关于MCU选型方面的知识，网站链接； http://bbs.ednchina.com/BLOG_ARTICLE_3031226.HTM 有据于此由来，自此来汇总一下在这方面所应用到的一些知识点的汇总，比如RESET复位脚（其中包含当中的时间计算），又如I/O口的驱动电流方面，又如在什么情况之下导致当中的MCU出现复位的现象。 关于复位电路的理解； 上面的这张图片只能说复位的一个概念，需要考虑的因素有两个地方，其中之一就是LDO的复位电压与MCU的复位电压，这两个都需要查询相应的datasheet。比如所用到的LDO芯片7A6150， 当然在这边还有几种不同的复位方式；比如软件复位，上电复位， 外部复位(External Reset) 它是影响时钟模块和所有内部电路,属于同步复位，但外部Reset引脚为逻辑低电平。在引脚变为低电平后，CPU的复位控制逻辑单元确认复位状态直到Reset释放。复位控制逻辑保持复位低电平状态，在额外512个时钟周期内。因为当复位引脚为低电平时与MCU执行复位命令是相互冲突的，因此复位引脚必须保证520时间周期内低电平才能保证外部复位被外部总线辨识出来。 上电复位（Power-on reset） 它是由外部总线产生的一种异步复位。单片机在电源电压VDD小于大约2.5V的时候复位，只要VDD电压不超过这个阈值，单片机就仍然保持复位状态。 电压跌落的时间大概在纳米级（如果一旦出现了，马上会复位）。因此监测上电复位不能单片机内部，因为小于这个电压单片机逻辑功能。 低电压复位（Low-Voltage Reset） 它是部分单片级内部监控器形成的异步复位，单片机电压小于一定触发值时，单片机开始复位。 低电压的复位电平是和供电电压相关的，会有一个波动： 软件复位（Software Reset） 它是由软件看门狗定时器超时引起的一个异步复位。如果要开启软件复位，必须要注意设置软件内部寄存器，使之有效。这个功能主要是用来防止程序跑飞。 双总线故障复位（Double Bus Fault Reset） 它是由双总线错误监视器产生的异步复位，它是总线错误的特殊状态会导致中止异常处理。 时钟丢失复位（Loss of Clock Reset） 它在参考时钟子模块消失的时候产生的同步复位。如果要使该复位有效，需要设置寄存器SYNCR。 关于更详细的外部Reset的资料可以这样描述（51单片机）： 为了确保良好的外部复位和上电复位，复位脉冲宽度必须足够宽，我们要考虑以下两个参数来确定复位脉冲宽度： tosc：振荡器才可达到Vih1或Vil1电压的时间。 tvddrise：电压VDD由10上升至90％的时间。 当这两个参数的条件得到满足时，还必须维持至少一定的机器周期来保证单片机内部的启动。 如果是不正常的复位的话： 如果要具体的计算，关于LDO的Reset可参考前面关于拉普拉斯变换的计算过程。 偷懒的话可以查表： 对于这张图片的红色标准的地方文字还是比较注意的地方，就是与MCU识别的时间搭好了相应的桥梁。 一般而言，我们的复位电路的应用如下所示； 计算公式如下图所示； 接下来需要思考的一个问题就是有哪些情况之下能够引起MCU复位呢？电源掉电，感性噪声，由于ESD相应的状况等等。 由于ESD引起的MCU复位效果； 曾经有一位彪悍的女同事，去了新单位后要确认一下静电电容到底能起多大的作用，能抗多大的静电，她把模块上所有的静电电容全部去掉，然后打一下静电，单片机就重启一下。 前面写过两篇文章是关于静电电容的 ESD电容问题 谈谈模块的的引脚布置和ESD问题 在这两篇以外举几个实例说明一下： 第一个例子是这样的，在打静电的时候测试EMC的性能（国内一般不这么BT的要做合成实验），出现了两个问题，第一个是单片机Reset了，第二个是某个频率段发射限值超标。 经过调查发现了原因是一个输出IC，由于是功率地，因此静电电容并没有直接打在地平面上，而是通过一根很长的PCB连线连接至地，因此阻抗比较高，这就变成了一跟天线，并且耦合至单片机，导致了单片机的Reset. 静电电容布线有三个原则，第一是必须给每个接插件引脚配上静电电容，第二是尽可能使得电容靠近接插件的引脚，第二个是尽可能使电容靠近地平面。 看下面一个例子，这次ESD直接把模块引脚打坏了 上例是在电容接到的是顶层一小块地，通过小的通孔连接后在内层连接地平面，距离过长，阻抗过高。 在某些极端情况下，ESD还会损坏MCU，特别是某些单片机有内部的稳压器，和它相近的IO口如果用来做输出而且没有很好的接静电电容（包括电容地没接好的情况）可能严重损坏单片机的稳压器，这会导致非常严重的结果。 还有一个值得注意的CAN的通讯口，一般高速的CAN不允许接大一些电容，这时候只能通过附加K级的电阻来防止信号耦合后损坏器件了，有钱的话可以选择TVS。 感性噪声引起MCU复位的情况； 曾经看到过一个很好的分析过程，把所有的内容都总结出来了。 在产品实验中，我们发现当部分电机启动的时候，单片机就Reset了。 继电器开关期间产生的噪声耦合到了MCU信号线路上。这种噪声引起了MCU电流注入/出，这种耦合噪音有足够高的转换率才会引起了微控制器的复位时的。 在系统设计的时候，是采用继电器来控制电机的，在出现问题后，我们做了实验，发现在继电器驱动电机过程中有以下的现象： -电动机的电感产生负电压尖峰。 -在继电器的开关期间，继电器触点上产生了一些地弹电压。 由于这些地弹，电池电压（9～16V）和电机产生的电压尖峰综合效应，导致了继电器触点上的电压高达-36V的（在继电器上压敏电阻器加装了之后）。 在产品设计的时候，有继电器未安装，然后在继电器输出线与地线之间存在高阻抗（86千欧）。 在上述条件下，驱动电机的继电器开关时产生的电压变化，电容耦合到未安装的继电器的输出线和反馈线，而他们是通过高阻抗连接到MCU的引脚上的。 这种耦合噪声电流注入/出到MCU，如果耦合噪音摆率足够高，将会导致微控制器的Reset。 两个因素导致此问题： 1）首先是不同PCB层电容耦合通道，有助于提高容性耦合。 2）其次是一些反馈线电容器连接到信号地平面，也有助于增加从功率噪音源的电子地平面的耦合。 经验教训： -良好的分配功率地和信号地，避免耦合噪声。 -避免在干扰源出来的任何线加电容到信号地。 -如果可能存在选择安装的器件，设置0欧姆电阻连接该器件的线到功率地，避免浮线。 对于以上的知识来说，从理论与应用现状详细的描述了MCU一些复位以及当中的应对策略。以上的几篇技术文章源自于玉龙兄的博客。@yulzhu

      大部分的FPGA和ASIC设计都是基于大量flip-flop或者寄存器的同步系统设计，所以所有这些同步单元的起始状态或者将要返回的状态是一个已知状态（罗辑‘1’或者‘0’）就显得非常重要。这一个功能通常都是由一个“reset”电路来完成。一个设计或者一个FPGA器件通常都使用或输入有一个或者多个复位信号，同时伴随一些其它控制逻辑电路来共同完成此“复位”功能。笔者希望探讨各种复位电路，同步的、异步的以及同步化的异步复位，分析这些不同复位电路的优缺点。展现实现这些不同复位电路的技巧，并使用Altera的TimeQuest时序分析器来对它们进行正确的时序分析。          我们通常意义上的同步电路通常是由两种复位方式来进行电路的复位，即同步复位和异步复位。同步复位的复位频率同步与寄存器的时钟域，而异步复位按性质，它影响或者说作用于寄存器的时刻和寄存器的时钟之间没有确定的时序关系。正因为如此，获取异步复位信号的时序关系是非常困难的。如前所述，我们还将讨论第三种复位，无法更好的为其命名，大家更多的时候叫其同步化的异步复位，就是一个异步复位被同步到系统时钟域，有时候大家也称这种过程为异步复位同步释放。这种同步化的异步复位，具有同步复位的好处，但是却没有同步复位的缺点；同时他们还避免了纯粹异步复位的缺陷。当我们详细地了解了这种复位结构后，我们将看到，这种同步化的异步复位应该是FPGA电路设计时复位电路的首选。

原文： http://blog.sina.com.cn/s/blog_6d784f8e0100t1kk.html 几乎每个FPGA设计都离不开复位，但很多工程师都没有真正关心过复位的设计。当你遇到一些奇怪的问题，也许就是由复位不当引起的。 对于同步单元，可以选择同步复位、异步复位或者不复位。有些人对不复位存有疑问，在ASIC设计中也许不行，但在FPGA设计中这个真的可以有。 一、能不用复位的就别用了。 reset，作为一个实际存在的物理信号，需要占用FPGA内部的route资源，往往reset的fanout又多得吓人。这就很容易造成route难度上升，性能下降，编译时间增加。因此，在FPGA设计中能省略的复位应尽量省略。 举几个我经常省略复位的地方，但不是绝对适用： 1.分频用的计数器 除非需要控制初始相位，否则分频用的计数器往往都是自由运行的，只要每个时钟加1就好。 2.移位寄存器 为了使pipeline配合正确，设计中经常会存在移位寄存器。这种情况下，你只要复位第一级寄存器，然后保持若干个周期，移位寄存器就被彻底复位了，而不用为每个bit都添加复位。移位寄存器不使用复位的又一个好处是可以利用SRL。 3.moore型状态机输出 对于那些moore型状态机的输出，你只要复位了状态机，下一个周期就会被复位。 不用复位可能会引起的一个问题是仿真时出现一堆的X。这个问题可以通过在HDL文件中为寄存器赋初值解决。   二、同步复位和异步复位 异步复位的优点： 不和时钟挂钩，EDA工具route起来更容易。 在没有时钟的时候也可以将电路复位。 输入时钟突然消失，为了防止逻辑混乱导致错误，那么就用异步复位吧，可以把PLL的lock信号当做异步复位。   异步复位的缺点： 无法进行时序分析，可能因为skew的问题造成逻辑错误。比如state 是一个状态机信号，由于异步复位的skew，可能造成state 比state 多复位了一个时钟周期。 毛刺会造成复位 有时上电可以工作，有时上电不能工作，看看是不是复位的问题。   同步复位的优点： 改善了异步复位的缺点 同步复位的缺点： 在高速时钟域比较难满足时序要求，或者为了满足时序造成编译时间增加。 总体来讲，在拿不准的情况下，用同步复位会更为可靠一些。同步复位要先将复位信号同步到该时钟域——打几拍时钟就可以了。   三、复位信号的选择 复位信号可能有多种源可供选择，常见的有外部的复位信号（例如复位电路产生的信号，push button， cpu的gpio等等），PLL的lock信号，内部逻辑产生的复位信号等等。 对于一般的逻辑，一起复位是没有问题的，但有时几个模块的复位最好有先后次序。 1.级联的锁相环 可以将第一级锁相环的lock信号经过几个时钟的延时，作为第二级锁相环的复位。 2.IODELAY和IDELAYCTRL 可以用IDELAYCTRL的rdy信号去复位IODELAY 3.GTP/GTX 这里面有一堆的复位，懒的专门去查一下资料了，回头有空再补吧。   四、总结 复位是容易被忽略的部分，但很重要，起始状态都不对电路还跑个屁啊。在给每个寄存器写复位的时候要想一下，不要想当然的加上if(!rstn)...否则最后发现设计工作不稳定，查原因可是很难的。  

It is the opinion of the authors that in general, every flip-flop in an ASIC should be resettable whether or not it is required by the system. Furthermore, the authors prefer to use asynchronous resets following the guidelines detailed in this paper. There are exceptions to these guidelines.   In some cases, when follower flip-flops (shift register flip-flops) are used in high speed applications, reset might be eliminated from some flip-flops to achieve higher performance designs. This type of environment requires a number of clocks during the reset active period to put the ASIC into a known state. Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flip-flop receive a reset, how will the reset tree be laid out and buffered, how to verify timing of the reset tree, how to functionally test the reset with test scan vectors, and how to apply the reset among multiple clock zones. 1.   Synchronous resets There are some advantages to using synchronous resets, but there are also disadvantages. The same is true for asynchronous resets.   The designer must use the approach that is appropriate for the design. Synchronous resets are based on the premise that the reset signal will only affect or reset the state of the flip-flop on the active edge of a clock. The reset can be applied to the flip-flop as part of the combinational logic generating the d-input to the flip-flop. If this is the case, the coding style to model the reset should be an if/else priority style with the reset in the if condition and all other combinational logic in the else section. If this style is not strictly observed, two possible problems can occur. First, in some simulators, based on the logic equations, the logic can block the reset from reaching the flip-flop. This is only a simulation issue, not a hardware issue, but remembers, one of the prime objectives of a reset is to put the ASIC into a known state for simulation. Second, the reset could be a “ late arriving signal” relative to the clock period, due to the high fan-out of the reset tree. Even though the reset will be buffered from a reset buffer tree, it is wise to limit the amount of logic the reset must traverse once it reaches the local logic. This style of synchronous reset can be used with any logic or library. Example 3 shows an implementation of this style of synchronous reset as part of a loadable counter with carry out. module ctr8sr ( q, co, d, ld, rst_n, clk);   output q;   output       co;   input   d;   input        ld, rst_n, clk;   reg      q;   reg          co;   always @(posedge clk)     if       (!rst_n) {co,q} = 9'b0;      // sync reset     else if (ld)      {co,q} = d;         // sync load     else            {co,q} = q + 1'b1; // sync increment endmodule Example 3a - Verilog code for a loadable counter with synchronous reset Figure 3 - Loadable counter with synchronous reset 1.1 Advantages of synchronous resets Synchronous reset will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. If a design is tight, the area savings of one or two gates per flip-flop may ensure the ASIC fits into the die. However, in today’s technology of huge die sizes, the savings of a gate or two per flip-flop is generally irrelevant and will not be a significant factor of whether a design fits into a die. Synchronous reset can be much easier to work with when using cycle based simulators. For this very reason, synchronous resets are recommend in section 3.2.4(2 nd edition, section 3.2.3 in the 1 st edition) of the Reuse Methodology Manual (RMM) . Synchronous resets generally insure that the circuit is 100% synchronous. Synchronous resets insure that reset can only occur at an active clock edge.   The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the flip-flop could go meta-stable. In some designs, the reset must be generated by a set of internal conditions.   A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clocks. By using synchronous resets and a number of clocks as part of the reset process, flip-flops can be used within the reset buffer tree to help the timing of the buffer tree keep within a clock period. 1.2 Disadvantages of synchronous resets Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock . A designer must work with pessimistic vs. optimistic simulators. This can be an issue if the reset is generated by combinational logic in the ASIC or if the reset must traverse many levels of local combinational logic. During simulation, based on how the reset is generated or how the reset is applied to a functional block, the reset can be masked by X’s. A large number of the ESNUG articles addressed this issue. Most simulators will not resolve some X-logic conditions and therefore block out the synchronous reset . By its very nature, a synchronous reset will require a clock in order to reset the circuit. This may not be a disadvantage to some design styles but to others, it may be an annoyance. The requirement of a clock to cause the reset condition is significant if the ASIC/FPGA has an internal tri-state bus.   In order to prevent bus contention on an internal tri-state a tri-state bus when a chip is powered up, the chip must have a power on asynchronous reset . 2 Asynchronous resets Asynchronous resets are the authors preferred reset approach. However, asynchronous resets alone can be very dangerous. The biggest problem with asynchronous resets is the reset release, also called reset removal. The subject will be elaborated in detail later. Asynchronous reset flip-flops incorporate a reset pin into the flip-flop design. The reset pin is typically active low(the flip-flop goes into the reset state when the signal attached to the flip-flop reset pin goes to a logic low level.) 2.1 Coding style and example circuit The Verilog code of Example 5a shows the correct way to model asynchronous reset flip-flops.   Note that the reset is part of the sensitivity list. For Verilog, adding the reset to the sensitivity list is what makes the reset asynchronous. In order for the Verilog simulation model of an asynchronous flip-flop to simulate correctly, the sensitivity list should only be active on the leading edge of the asynchronous reset signal. Hence, in Example 5a, the always procedure block will be entered on the leading edge of the reset, then the if condition will check for the correct reset level. module async_resetFFstyle (q, d, clk, rst_n);   output q;   input   d, clk, rst_n;   reg     q;   // Verilog-2001: permits comma-separation   // @(posedge clk, negedge rst_n)   always @(posedge clk or negedge rst_n)     if (!rst_n) q = 1'b0;     else         q = d; endmodule Example 5a - Correct way to model a flip-flop with asynchronous reset using Verilog 2.2 Advantages of asynchronous resets The biggest advantage to using asynchronous resets is that, as long as the vendor library has asynchronously reset-able flip-flops, the data path is guaranteed to be clean. Designs that are pushing the limit for data path timing, cannot afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets. Of course this argument does not hold if the vendor library has flip-flops with synchronous reset inputs and the designer can get Synopsys to actually use those pins. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. The code in Example 7 infers asynchronous resets that will not be added to the data path. module ctr8ar ( q, co, d, ld, rst_n, clk);   output q;   output        co;   input   d;   input         ld, rst_n, clk;   reg     q;   reg           co; always @(posedge clk or negedge rst_n)     if       (!rst_n) {co,q} = 9'b0;      // async reset     else if (ld)      {co,q} = d;         // sync load     else              {co,q} = q + 1'b1; // sync increment endmodule Example 7a- Verilog code for a loadable counter with asynchronous reset Figure 4 - Loadable counter with asynchronous reset Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. The experience of the authors is that by using the coding style for asynchronous resets described in this section, the synthesis interface tends to be automatic. That is, there is generally no need to add any synthesis attributes to get the synthesis tool to map to a flip-flop with an asynchronous reset pin. 2.3 Disadvantages of asynchronous resets There are many reasons given by engineers as to why asynchronous resets are evil. The Reuse Methodology Manual (RMM) suggests that asynchronous resets are not to be used because they cannot be used with cycle based simulators. This is simply not true. The basis of a cycle based simulator is that all inputs change on a clock edge. Since timing is not part of cycle based simulation, the asynchronous reset can simply be applied on the inactive clock edge. For DFT, if the asynchronous reset is not directly driven from an I/O pin, then the reset net from the reset driver must be disabled for DFT scanning and testing. This is required for the synchronizer circuit shown later. Some designers claim that static timing analysis is very difficult to do with designs using asynchronous resets. The reset tree must be timed for both synchronous and asynchronous resets to ensure that the release of the reset can occur within one clock period. The timing analysis for a reset tree must be performed after layout to ensure this timing requirement is met. The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost. Another problem that an asynchronous reset can have, depending on its source, is spurious resets due to noise or glitches on the board or system reset. See section later for a possible solution to reset glitches. If this is a real problem in a system, then one might think that using synchronous resets is the solution. A different but similar problem exists for synchronous resets if these spurious reset pulses occur near a clock edge, the flip-flops can still go metastable. This article abstracted from CummingsSNUG2002SJ_Resets , the original author is Clifford E. Cummings and Don Mills.      

excerpt from http://forums.xilinx.com/t5/PLD-Blog/That-Dangerous-Asynchronous-Reset/ba-p/12856 Try to think in terms of ‘global’ simply meaning ‘everything’ or ‘all’ regardless of scale. If I develop a macro that contains 100 flip-flops and every one of them is connected to a reset signal then we can say that the macro contains a global reset. If I then instantiate that macro in a design 20 times and I connect all the reset inputs back to one reset input pin there will be 2,000 flip-flops all connected to the same global reset even though at the top level it only looks like there are 20 loads. So it isn’t how it looks depending at what level you view it but the fact that you have just blindly connected every reset together at any level that you look at it. The danger is that what seems small at any one level all adds up to be something big and that large fan-out will result in larger delays and skew both of which contribute to the nasty stuff we are trying to avoid. In contrast, a local reset is where only those flip-flops that need to be reset in a particular way are treated in isolation. For example, I may have recognized that of the 100 flip-flops in my macro, 4 were used to form a state machine critical to reliable operation so I provided them with a carefully controlled synchronous reset generated locally (probably a signal generated as a consequence of the release of the ‘global’ asynchronous reset).  May be I left the other 96 flip-flops connected to the ‘global’ reset just for a clean simulation (or to satisfy that unnecessary design review item!). Back in the big design I would then have 1,920 flip-flops connected to the ‘global’ reset but providing as long as the input reset signal is clean that would be fine. However  the complete design also contains 20 carefully controlled local resets which do matter. Now there may be cases in which the  local reset needs to connect to tens or even hundreds of flip-flops so you shouldn’t take fan-out as a measure of what is local or global. The key difference is that in any localized reset you maintain precise control over what happens because you care about it. In practice, it just gets very difficult to maintain that control if the fan-out is too high. If it were easy to have precise control over all flip-flops in the device then we wouldn’t be having this discussion. To make it really simple….. Local means you care and global means you don’t.