所需E币: 4
时间: 2020-1-15 14:32
大小: 140.46KB
FPGA应用举例FPGA应用举例七段译码器LIBRARYIEEE;USEENTITYseven_vISPORT(D:S:ENDseven_v;ARCHITECTUREaOFBEGINPROCESS(D)BEGIN???ENDPROCESS;ENDa;IEEE.STD_LOGIC_1164.ALL;CASEDISWHEN0=>SSSSSSSSSSS半加器-(不考虑低位的进位)LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;ENTITYhadd_vISPORT(A,B:INSTD_LOGIC;S,C:OUTSTD_LOGIC);ENDhadd_v;ARCHITECTUREaOFhadd_vISSIGNALtemp:STD_LOGIC_VEC……