标签: protocol

The JESD204 serial interface standard -- the latest version of which is the JESD204B revision -- was  developed under the auspices of the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters, such as analog-to-digital converters and digital-to-analog converters, and other devices, such as SoCs and FPGAs.   High-speed serial interfaces like JESD204B have several advantages over their traditional parallel counterparts. In addition to minimizing the I/O pins used in chip-to-chip communication, for example, they ease routing congestion at the board level.   One downside of the JESD204B standard is the fact that it uses 8b/10b encoding, in which each eight-bit data byte is converted into a 10-bit character/symbol for transmission to achieve DC balance and provide sufficient state changes to allow clock recovery. (The clock is embedded in the signal.) This extra pair of bits-per-byte results in a 25% overhead for each character; to put this another way, 20% of the channel is consumed by the 8b/10b encoding overhead.   For many users, this overhead may not be a problem. However, for designers who are pushing the bounds and working on the bleeding edge of what is possible, this overhead may be a bit too much. (I'm sorry; I couldn't help myself.)   I bring this up because I was recently chatting with my chum Adam Taylor, who works at e2v in the UK. If the truth be told, it's difficult to pin down exactly what e2v does from its website. All I know from my conversations with Adam is that it is big in imaging -- especially imaging sensors for space applications. When I was glued to my television watching the Rosetta space probe's Philae lander module approach the comet 67P/Churyumov–Gerasimenko a few weeks ago, for example, part of the news report showed a room of folks at e2v cheering, because e2v sensors helped guide Rosetta to its destination and capture the most amazing images ever seen of a comet. But I digress.     During our chat, the topic of high-speed chip-to-chip communication came up, including the JESD204B standard. Adam asked me if I'd ever heard of the open-source ESIstream protocol. When I admitted that I was sadly uninformed on this little rascal, he arranged for me to chat with Nicolas Chantier, e2v's technical expert on this topic.   Here's what I learned in a nutshell. First of all, when it comes to e2v's microwave communications products, many of the chips it designs are based on a silicon-germanium alloy. This material is great for the analog/microwave portions of the design, but it's not as attractive for implementing large digital functions. Though e2v did look at implementing JESD204B cores on its silicon-germanium chips, it decided that this standard was overly complicated, required too much digital logic to implement, and carried too much overhead with regard to the 8b/10b encoding it used.   Way back in the mists of time we used to call 2006, e2v was experimenting with chip-to-chip communications for some radio astronomy application that was using analog-to-digital conversion running at 20 gigasamples-per-second. To implement this, it developed its own high-speed serial interface protocol.     This effort has evolved over the years into something e2v now calls the ESIstream Protocol , where "ESI" stands for "efficient serial interface." Though it was developed by e2v, ESIstream is not proprietary -- e2v is offering it to the community at large as a completely open protocol.   The ESIstream protocol uses a 14b/16b encoding scheme, which results in a ~14% overhead for each character, as opposed to 25% for JESD204B. Only 12.5% of the channel is consumed by the 14b/16b encoding overhead, as opposed to 20% of the channel using JESD204B's 8b/10b scheme. The big takeaway here is "less overhead = more useful data."   Furthermore, the digital logic required to implement an ESIstream core is significantly smaller and simpler than its JESD204B equivalent, making it easier to implement these cores on e2v's semiconductor substrate of choice (silicon-germanium).   If you visit the Downloads page on the ESIstream website , you can download presentations and specifications. My understanding is that a raft of additional documentation -- including a bunch of implementation examples combined with corresponding VHDL code -- will be made available in the very near future. (I'll ask Adam and Nicolas to comment on this below.)   In the meantime, are you using or are planning to use JESD204B for your high-speed chip-to-chip communications? If so, do you think you'll take a look at the ESIstream protocol as an alternative?