标签: library

  首页     硬件设计     Cadence Allegro   PCB封装神器-OrCAD Library Builder下载安装及**指南 2015 09-12 PCB封装神器-OrCAD Library Builder下载安装及**指南   xfire   Cadence Allegro ,  Cadence OrCAD  围观 529 次   16 条评论  编辑日期：2015-09-12  字体： 大   中   小 OrCAD Library Builder 是Cadence公司旗下的原理图符号（schematic symbol）及PCB封装库（PCB footprint）自动创建神器，其可以根据元器件Datasheet里边对元件的管脚描述信息，自动创建symbol及匹配的 PCB footprint 封装。不是说Allegro自带的元件库坑妈，用这个吧，其预置了大部分常用的PCB封装库，而且是符合IPC-7351国际标准的，使用 OrCAD Library Builder 自动创建元器件封装库，可以省却我们很多的时间，并且是符合IPC-7351标准的封装。其实Allegro麻烦就麻烦在建封装上了，分的太细，用OrCAD Library Builder，啪啪啪，轻点几下鼠标，一个标准的封装即可完成。pcb攻城狮值得拥有。           OrCAD Library Builder下载地址： http://www.mr-wu.cn/cadence-orcad-allegro-resource-downloads/   OrCAD Library Builder 官方介绍视频：       OrCAD Library Builder 安装视频教程：         百度视频分享：   http://pan.baidu.com/s/1c0sIk16               原创文章，转载请注明：  转载自  吴川斌的博客  http://www.mr-wu.cn/  本文链接地址:  PCB封装神器-OrCAD Library Builder下载安装及**指南 http://www.mr-wu.cn/pcb%e5%b0%81%e8%a3%85%e7%a5%9e%e5%99%a8-orcad-library-builder%e4%b8%8b%e8%bd%bd%e5%ae%89%e8%a3%85%e5%8f%8a%e7%a0%b4%e8%a7%a3%e6%8c%87%e5%8d%97/

ABSTRACT The CAD library is the starting point that affects every process from PCB layout through PCB manufacturing and assembly. There are dozens of things to consider when creating a CAD library. Each can directly affect the quality of the part placement, via fanout, trace routing, post processing, fabrication and assembly processes. Yet, they are often overlooked. This paper, the first in a series dedicated to CAD library quality, describes each aspect you should consider when creating Molded Body Component library parts. It also describes the  impact  each feature has in the PCB process.   CAD LIBRARY PARTS There are three types of CAD library parts; plated through hole (PTH), surface mount devices (SMD), and a combination of the two technologies. SMD and PTH CAD libraries are distinctively different but the same basic rules apply to both technologies: “snap” and “round-off” CAD library land (pad) shapes to 0.05 mm increments. All of the component land patterns represented in this document are included in the xDX Land Pattern Creator that comes free with every seat of PADS® PCB  design software. THE UNITS Today, 90% of all component manufacturers list their component package dimensions in metric units. For example, Texas Instruments only provides metric units for their component packages. TI is following the metric mandate by all world standards organizations and 99% of all world governments. Accordingly, this paper utilizes metric units for CAD library development. THE CALCULATIONS The examples in this document are calculated utilizing the nominal environment as defined in IPC-7351B’s standard 3-tier CAD library system: See Figure 1. 1. Level A = Most – for military and medical applications. 2. Level B = Nominal – for controlled environment desktop. 3. Level C = Least – for cell phones and hand-held devices. MOLDED BODY COMPONENTS With the exception of chip components, the next  most -popular component family on a PCB  design layout is the molded body tantalum capacitor (CAPM). The CAPM components have an “L-Bend” component lead form. Most molded body tantalum capacitors are metric by default, including their standard EIA names: 3216–3.2mmX1.6mm 6032–6.0mmX3.2mm 7243–7.2mmX4.3mm  7343–7.3mmX4.3mm The common component families that use the molded body package are: Non-polarized capacitors Polarized capacitors Diodes Resistors Inductors Fuses LEDs Figure 2 provides the 6032 component and land pattern dimensions. A rule was broken to create this land pattern. Instead of a 1.0 mm land placement round-off, a 2.0 mm land placement round-off was used to snap the land centers on a 0.5 mm grid from the center of the land pattern. When the land pattern is placed on a 0.5 mm grid, the land centers fall on a 0.5 mm grid. This improves the via fanout seen in Figure 4. Figure 3 illustrates the silkscreen and placement courtyard rules and sizes. The illustration shows the component leads on top of the lands for graphic representation. Figure 4 illustrates the via fanout for a 6032 tantalum capacitor. If you are going to use the same-size via to maintain trace/space compatibility with the rest of the PCB layout, at least two vias are recommended. Placement of these vias is critical for reducing impedance and increasing capacitance. It’s important that the vias be placed as close as possible to the capacitor terminal leads. In Figure 4, the two vias coming out the side are 0.15 mm away from the terminal lead. The vias coming out the ends on the land pattern are 0.75 mm away from the terminal leads. Although that’s five times farther away than the vias coming out the sides, some EE engineers will request all four vias. Since all the traces and vias are snapped to a 0.5 mm grid, this makes copy/paste much easier to manually fan out all of the 6032 molded body capacitors. The dot grid display is 1 mm and the land pattern is placed on a 0.5 mm grid. All the vias in this illustration fall on a 1 mm snap grid. For the 7343 molded body tantalum capacitor, Figure 4, it is recommended that a larger via size,with a 1 mm land, 0.55 mm hole size, and 1.3 mm plane anti-pad, be used. The larger via can carry more current and you only need two (but the EE will ask for a 3rd one). The illustration in Figure 5 snaps all the vias to a 1 mm grid system. These vias are twice the size of the previous vias but the same trace/space rules apply. The display grid is 1 mm. Because the land pattern, traces, and vias are on a 1 mm snap grid, this improves the copy/paste feature for manual fanout of all of the 7343 molded body components in your PCB layout. SOME MOLDED BODY COMPONENT FAQ’S Q: Do multiple and larger vias affect CAPM soldering? A: The GND PWR vias have a direct plane connection (no thermal pattern in the via hole). The thermal relief in this fanout is the trace between the Land and the via so you can have as many vias as you want as long as the total sum of the trace widths + via hole diameters connecting the land and vias does not exceed 60% of the land diameter. This is noted in the IPC-2221 and 2222 documents where it says that the total “spoke widths” should not exceed 60% of a hole diameter for a through-hole lead to prevent a cold solder  joint . So be careful that you do not use multiple vias with wide trace widths. Two vias are typically recommended for bulk tantalum capacitors. Three vias are shown in Figure 5 to illustrate the preferred via locations. Having two vias that come out of the sides of the land pattern is common because they are closer to the component leads. It is not recommend to have the vias come out of the ends of the land pattern because they are further away from the component leads. The closer the via is to the component lead, the greater the capacitance and reduced inductance. This via location tip only applies to bypass decoupling capacitors and discrete parts that are attached to the planes. It is also typical to see trace widths that are the same width as the via diameter. A 1.0 mm via diameter would have a 1 mm trace width. The picture shows a 1 mm via with a 0.5 mm trace width. Q: For a square land, what “diameter” should be used for calculating the 60% maximum spoke width? A: There are no rules for calculating spoke width for SMD lands. The 60% rule is in relation to the “hole diameter.” Q: Do the two vias on the sides (Figure 3) leave a solder web between the via and the pad? A: The vias coming out the “side” (rather than the top and bottom) of a chip capacitor to get the via as close to the component lead as possible to increase capacitance and decrease impedance. Ultimately, via-in-pad under the component lead will result in the best high-speed performance and highest component-packing density. “Bottom only” component leads (like all the grid arrays: LGA, BGA, CGA) and fine pitch will drive via-in-pad to become more popular. The fact is that if you put via-in-pad on one part, you might as well do it on all parts because the fabrication cost does not change. i.e.: once you start to use via-in-pad, the fabrication cost automatically goes up, but it does not increase with the number of via-in-pads (unless you exceed several thousand holes). Each manufacturer is different. Q: If there were no solder mask between the via and the pad, would solder migration be a concern? A: All vias, on the same layer as the components, should be “tented” with solder mask. If there are only components on the top layer, then only the top-layer vias need to be tented. If there are components on both sides, then both sides should have tented vias. CONCLUSION Every design aspect should be considered when creating molded body components and the  impact that each feature of the land pattern has in the PCB  design  process. The land pattern is the starting point that affects every process from PCB layout through PCB manufacturing and assembly. There are dozens of things to consider when creating a CAD library that are often overlooked; this paper discussed the factors to consider when creating molded body component library parts. Each factor can directly affect the quality of the part placement, via fanout, trace routing, post processing, and fabrication and assembly processes. 原创文章，转载请注明：  转载自 吴川斌的博客 http://www.mr-wu.cn/  本文链接地址:  PCB Design Perfection: The CAD Library Series Part 1: Molded Body Componentshttp://www.mr-wu.cn/ pcb - design -perfection-the-cad-library-series-part-1-molded-body-components/

This time I would like to share a few recently-drawn Altium libraries. They are (1) Micro SD Card Slot (SMT) (2) MiniUSB Socket (SMT) (3) FPC 20-pin, 1mm pitch Socket (SMT)   Important note: The schematic symbols or footprints of (1), (2) and (3) may vary due to different manufacturers and different batches. Double check the suitability before use.   (1) Micro SD Card Slot The footprint was created for a surface-mount micro SD Card slot from Taobao. This slot is one with spring inside. When the micro SD card is inside the slot, press it again will release the card. (自彈) Fig. The micro SD card slot from Taobao   Since SD cards can be accessed through SPI or SDIO protocols, the symbol was created with marked to the pin names. Fig. The schematic symbol   There is a pin, this pin will be shorted to the casing when the card is inserted. So an external pull-up resistor and connecting the casing with Ground(VSS) are suggested to detect the card by I/O input with MCU.   Fig. Footprint for the micro SD slot   (2) MiniUSB Socket This is a simple mini USB socket Fig. The mini USB Socket   Fig. Mini USB symbol   Fig. mini USB Socket footprint   (3) FPC 20-pin side-mount socket FPC Cable is widely used to connect PCBs on movable mechanical parts, like scanner and printers. Fig. A scanner using FPC cable to link the scan sensor (Source: www.truetex.com)   Fig. The 20-pin, 1mm pitch FPC sockets (side mount)   Fig. 20-pin, 1mm pitch FPC Cable Fig. The FPC 20-pin symbol   Fig. The FPC 20-pin, 1mm pitch side-mount socket   Although the above symbols and footprints are not complicated to draw, I would like to share them here because I think sometimes it is quite time-consuming to draw the footprint of a new component, especially without the CAD dimension drawings on hand. In that case, we have to measure the dimensions first and then draw the footprint carefully. But if there is libraries of similar parts, simple modifications on the existing libraries (like modifying the number of pins in the above FPC socket) would fit the new component - need to draw from zero. So it could be very helpful to others if we draw the libraries and then share them to others :)

    1、目标库（targe_library）：一般就是std cell db；放的是标准单元工艺库； 是你的综合目的库，存放的是你索要映射的逻辑单元。一般为standard cell library io cell library 的type ；是DC在mapping时将设计映射到特定工艺所使用的库，就是使用目标库中的元件综合成设计的门级网表。   2、连接库（link_library）：指定压焊块工艺库名称和所有其他的宏单元（RAM、ROM等）；除了std cell，还有IO ,MACRO ,MEMORY db；一般为宏单元等其他库；一般可以放算法库和设计库等，比如DW；是提供门级网表实例化的基本单元，也就是门级网表实例化的元件或单元都来自该库。连接库定义为标准单元的db格式的库文件加上pad db格式的库文件，加上ROM，RAM等宏单元库文件。   3、符号库（symblo_library）:包含工艺库中的单元图形表示的库名称。使用DV时，用于表示门电路原理图。如果忽略这一设置，DV会使用一个名为“generic.sdb”的通用符号库来生成原理图。如果你设置了symbol_library，但是假如你的单元的工艺库和符号库不匹配，DV会拒绝你的符号库，而调用通用库中的单元符号。   4、简单地讲，所有用到的库都要放到link_library，因为DC自动到那里去找。只有作综合用的库放在target_library,象ROM,PAD等不用synthesis的就不要放进去了。   5、link_library列表中应包含目标库名，这在DC中读取门级网表是很重要的。如果连接库列表中不包含目标库名，DC就不能连接网表中已经映射的单元，在这种情况下，DC会生成表示其不能解析网表中单元的警告。   6、 link_library 可以包含旧的工艺库名称，而 target_library 可以包含新的工艺库名称。   7、简单来说link library就是解决实例化引用的，如果实例化的就是一个与非门，DC就从target library中找到，如果例化的是一个fifo，DC就从fifo的库中找到，如果例化的是一个模块，DC就从内存中找到，因为这个模块的代码在编译过程中已经读进内存中去了。   8、pt和fm工具只有link_library，DC使用变量 link_library，而PT使用link_path，除了名称和格式不一样之外，这两个变量的应用时相同的。PT是一个门级静态时序分析器，它只是用于结构化门级网表，因而，PT不使用变量target_library。      

The STM8S/A Standard Peripherals library provides a rich set of examples covering the main features of each peripheral.   Almost examples run on all supported STM8S/A devices. However some of them are device specific due to peripheral availability constraint.  All the examples are independent from the software tool chain. These examples run on STMicroelectronics STM8/128-EVAL evaluation board and can be easily tailored to any other supported device and development board.  Only source files are provided for each example and user can tailor the provided project template to run the selected example with his preferred tool chain. 上面是官方给我的STM8外设固件库的使用说明，通过使用固件库，就可以很方便的上手了。一方面掌握寄存器配置的同时，通过使用固件库，也不失为一种好的途径。跟STM32有得一拼啊。