标签: serial

Serial communication has long been an effective means of transmitting data with a minimum set of wires across long cables and different media. The serial data links that are in use vary in both transmission speeds and protocols. New serial protocols are constantly being brought to market. FPGAs with embedded SERDES blocks coupled with reconfigurable logic are effective in handling a wide range of serial communication protocols. FPGA blocks typically embed high-speed analogue SERDES blocks that work within a fixed range of data rates. Because of internal PLL operating range limitations, the lower cut-off data rate with these high-speed SERDES blocks is typically around 1,000 Mbit/s. However, there are several serial protocols that operate below that. Take the commonly used IEEE1394 protocol that extends its operating data rate from 400 Mbit/s to 3.2 Gbit/s. To support the lower data rates of such protocols, an oversampling technique can be used. In this technique, each data bit is sampled in multiple clock cycles before being transmitted. For instance, to transmit a 400 Mbit/s data rate over a serial link that supports 1 Gbit/s or above, each bit can be sampled three times and spread over three clock cycles. This is called 3x oversampling. Using this technique, lower data rates can be transmitted while the SERDES PLL continues to run within its valid operating range. On the receiver side of the SERDES, after the clock data recovery (CDR) unit locks on to the incoming data stream and starts to recover received data, the receiver side of the logic in the FPGA looks for transitions in the received data bits. When a transition between a 1 and a 0 is initially found, the received bits from that point onward are downsampled, and the oversampled data is brought back to the original rate. In the 3x oversampling example, three consecutive 1s are downsampled to a single 1 bit, while three consecutive 0s are downsampled to a single 0 bit. When using this technique, the CDR unit is still performing clock and data recovery. In some FPGA oversampling techniques, the CDR is providing only a high-speed sampling clock to the FPGA. The FPGA must then determine the edge boundaries of the multiple samples of bits of data. Due to the asynchronous nature of the data to the high-speed sampling clock, the oversampling must be done at least five times the data rate clock. By using the CDR unit to recover the data and create a synchronous sampling clock, the FPGA clock rate can remain at three times the data rate, thereby keeping the power down for the entire interface. Most serial protocols use comma characters for alignment along with 8b/10b or other encoding methods. On the transmit side, the oversampling should be performed after inserting comma characters and on the encoded data stream. On the receive side, the comma detection and aligner circuits need to be employed after downsampling the received data. Such a setup is possible while using FPGAs that employ SERDES blocks with reconfigurable logic. The SERDES can be used to transmit serial data rates across wide ranges, while the FPGA logic can be used for oversampling and other functions. Have you used these techniques or others in your designs? Please share your experiences in the comments below. Chowdhary Musunuri is Director for Engineering Solutions, SoC Product Group at Microsemi .  

Serial digital interface(SDI) is a standard for high quality lossless digital video transmission.   Depending on the data rate there are different variants of SDI: - SD-SDI carries NTSC/PAL video data with a data rate of 270Mbps - HD-SDI carries High Definition videos with a data rate of 1.485Gbps - 3G-SDI carries 1080p50 videos with a data rate of 2.97Gbps - Dual - Stream SDI carries two independent HD video streams in a single link. This results in a data rate of 2.97Gbps   The greatest advantage of SDI is being able to transfer high- definition video signals without any loss of quality. This is due to the fact that the video is transferred in uncompressed format. A video network based on SDI can be easily put together with a readily available 75 ohm co-axial cable between a transmitter and a receiver. Because of these benefits, SDI is rapidly becoming the leading video format for digital video transmission.   One of our recent designs involved an SDI transmit and receive, both working at 3G data rate. The scope of our project required that we output processed video streams on the SDI interface. We integrated a high-end video processor from TI along with a Spartan – 6 FPGA from Xilinx for this. The SDI physical interface was implemented by integrating an SDI core inside the FPGA. The SDI core mainly uses two clocks, one a Reference clock and  the other a pixel clock. The reference clock is a fixed LVDS clock input while the pixel clock is the one to which the parallel video data is synchronized from the processor. For proper functionality, SDI core expects both data and reference clocks to be in complete phase synchronization.   The main challenge that we faced in bringing up SDI-TX was in achieving synchronization between the processor’s pixel clock and the reference clock fed to the SDI core. To mitigate this, we added a FIFO in FPGA and used an internally generated clock inside the SDI core, as a FIFO read clock, with pixel clock being used as FIFO write clock. Although this resulted in phase synchronization, there were frequent underflow and overflow of FIFO due to minute frequency jitter among these clocks. To eliminate this, we had to find a common clock source for the pixel clock and the SDI core’s reference clock . To accomplish this, we connected a clock from FPGA, generated from SDI core reference clock, to an auxiliary clock input of the processor. Since the processor now derived the pixel clock using this auxiliary clock input, the FIFO overflow/underflow issue got resolved. Synchronization with the processor was not an issue for the SDI-RX path since the SDI-Core in itself generates pixel clock.   The second major problem that we encountered was with respect to Dual-stream SDI. To give DS-SDI output, SDI core requires two parallel video inputs which are frame synchronized. In our design, the processor was giving out two parallel video outputs to FPGA and it was not possible to achieve frame synchronization at the source. Thus, the FPGA had to align the two video frames before routing it to SDI core. Here we used a DDR3 connected to FPGA to achieve frame alignment. One of the incoming video stream data was written to DDR3 continuously beginning from the start of the frame, along with checking for start of frame in second video stream. Once the start-of-frame in second video data is detected, this stream along with the first stream, is sent to SDI core for generation of DS-SDI. The data from the first stream is not live in the sense that a stored frame is being read back from DDR3. It has to be noted that the size of the DDR3 memory must be big enough to store one complete frame.   The design of an SDI system not only involves proper understanding of the SDI core architecture but also careful high-speed design. In addition, a major aspect to getting the interface to work flawlessly is a robust PCB design. This becomes extremely important since the data rate in SDI line can go upto 2.97Gbps. The main objective of PCB layout design is to achieve uniform impedance along the entire trace. This included careful selection of series components on the trace, trace width selection, trace separation for differential lines etc. Since our design involved both SDI receive and transmit, we made sure that there was good enough separation between TX and RX circuits to avoid any interference.   - Suresha N S, Harshith Kasyap and Alagappan Ramanathan

以Acute TL2236逻辑分析仪进行串行闪存量测方案 在许多的电子产品中都有使用串行闪存(Serial/SPI Flash)的需求，它有较简单的控制程序与电路以及可靠的储存能力，使它倍受青睐。因此，常被用于电子产品里放置较关键的开机程序(Boot code)或系统设定数据(System setting)。 每当系统启动时，Serial Flash 就会忙碌起来，尽快的把储存在里面的程序或数据加载系统内。但越来越复杂的命令组合以及命令差异，使得开发与除错工作变得更加困难。本文将会介绍使用逻辑分析仪来进行 Serial Flash 的量测工作。 单线模式译码 早期的 Serial Flash 使用 SPI 总线架构，定义了 4 根与命令数据传输有关的脚位分别是 Chip Select (CS)、Clock (SCK) 、Data In (DI) 、Data Out (DO)。传输时，由 DI 将命令或数据传入 Serial Flash，而 DO 将数据读出。如图一所示。一般称之为单线模式(Single mode)。 * JEDEC Standard No.216: (x-y-z): 标示Serial Flash  I/O 的模式，分别为命令码(opcode x)，地址(address y)，数据(Data z)。 用户若需量测 Serial Flash 总线时，只需使用具有 SPI 总线的仪器或工具，就可以将单线模式之Serial Flash 命令/地址/数据解出。这是业界行之多年的作法。 双线及四线模式译码 有鉴于电子产品越来越需要大容量的储存空间，Serial Flash 容量也顺应扩大。 储存容量扩大之后衍生而来的问题是，读取数据的时间越来越长，于是 Serial Flash 开始提高其工作频率，藉由较高的传输频率，以缩短传输数据的时间。 但这样还是不够快，因此进一步发展出现所谓双线模式(Dual mode)如图二，与四线模式(Quad Mode)，如图三的 Serial Flash。其总线传输的架构，已渐渐与单线模式之 SPI 架构不同，也使原有的 SPI 仪器或工具用在此类 Serial Flash 的总线除错工作开始出现困难。 在各厂商所推出的Serial Flash，更增加了多种不同数量的命令与数据组合，若没办法识别 Flash 命令的软件工具，将很难看出总线的内容。因为这样的需求，使得具有支持 Serial Flash 总线分析的逻辑分析仪成为不可或缺的工具，它可协助分析这种多样性的讯号。他可以随着 Flash 命令的改变，而做出相应的分析。 使用逻辑分析仪分析不同命令组合分析  A. 随着命令的不同，Serial Flash 会以不同数量的传输线工作 下列的范例，列举了几个不同形式结构的 Serial Flash 结构，可以一窥命令差异所带来的影响。  范例一：如图四所示，此命令 3Bh (Fast Read Dual I/O) 是个 (1-1-2) 结构的命令，输入命令与地址时只需要使用 1 条线，但数据输出时为双线。图例可以看出，传送命令须使用 8个 Clock，但接收数据只需 4 个 Clock。 图四 Flash 命令 3Bh 波形画面 (1-1-2)  范例二: 如图五所示，此命令 EBh (Fast Read Quad I/O) 是个 (1-4-4)结构的命令，输入命令使用 1条线，但地址与数据皆为 4 条线。图例可以看出，传送命令须使用 8个 Clock，但传送地址与接收数据只需 2 个 Clock。 图五 Flash 命令 EBh波形画面(1-4-4) 范例三：如图六所示，此命令 6Bh(Fast Read Quad Ouput)是个 (1-1-4) 结构 的命令，与地址时只需要使用 1 条线，但数据输出时为 4线。图例可以看出，传送命令与地址须使用 8个 Clock，但接收数据只需 2 个 Clock。   图六 Flash 命令 6Bh波形画面(1-1-4)  B. 更胜于 SPI 总线分析的功能 如图七所示，可看出有别于 SPI 数据输入与输出分成两条线时，不容易判别何时是数据输出的时间点。在光标A所在位置，就是 Serial Flash 开始输出数据的地方，从信道 SPI-DO 查看时必须自行数到第5个Byte 才算是数据输出点。  有时候 Serial Flash 在输入时还会安插 Dummy Byte，这样就更增加查看输出讯号的困扰。但若采用 Serial Flash 总线分析，藉由清楚的文字说明，就可以清楚的标示来数据的意义。   图七 Serial Flash(SFlash) 与 SPI (SPI-DI, SPI-DO) 总线分析比较  C. 效能提升模式 PEM (Performance enhance mode)的分析 为了加快 Flash 数据传输速度，在进入效能提升模式后，读取数据不需要再下命令；因此第一笔输入数据即为地址，而非命令。此法可减少下命令的次数，以达到加速的效果。  由于效能提升模式的设定参数，都是包含在 Dummy byte 里面。而且，各 厂商之设定(Set)与取消 (Reset) 规则也不同，也使得判读上困难许多。如图八所示，就是一个设定进入效能提升模式波形范例。 图八 即使Flash 进入效能提升模式，地址与数据也可正确地被分析出来  D. 逻辑分析仪 Serial Flash 分析设定画面 在设定画面左上角，可选择不同的 Flash 制造商及Flash型号。分析软件已经收录 Flash Data Sheet 数据，作为分析的参考，实时没有完全对应到型号，也可以拿兼容的型号来解碼都是可以的。  设定画面左侧则是信道设定及译码分析设定，有些设定值如 QPI(Quad Peripheral Interface)模式，在系统启动时就被软件设定好。这样的话使用者也可以透过手动的方式指定逻辑分析仪分析，就可以无误的解析出数据，如图九所示。 图九 Serial Flash 分析设定画面 E. 完整的Serial Flash分析报告 不管是多线的组合或是效能提升模式都可藉由完整的报告，将命令、地址、提升模式设定值、数据(十六进制与 ASCII) 都可详细的呈现。这样，就可快速的得知分析的内容，尽速的找到问题点，如图十所示。 图十 Serial Flash 分析报告 利用 SPI 触发来进行讯号定位 虽然 Serial Flash 会有多线的组合，但仍有一部分的命令及地址是单线模式。因此，可利用逻辑分析仪的 SPI触发功能协助讯号定位。图十一即是使用 SPI 触发功能，主要就是把将命令及地址数据输入。这样，就可以针对特定条件进行触发。 图十一 设定 SPI触发功能以触发 Serial Flash 命令0Bh，地址 12h 23h 45h. After CS 打勾的意思是指从 CS go low 之后就开始判断  在使用SPI触发的同一个时间，若可以将逻辑分析仪与示波器堆栈，就可以使用逻辑分析仪替示波器定位，如图十二所示。这样，问题分析就同时具有 Serial Flash 数字与模拟讯号的分析，更加的详尽清楚。透过档案共享，亦可使整个工作团队共享撷取的讯号，加快分析问题的速度 图十二 结合逻辑分析仪与示波器来看 Serial Flash 总线讯号   结语  藉由本文的介绍，Serial Flash 总线分析工作将可藉由逻辑分析仪触发及软件的配合。使原本复杂的命令组合变化及命令的定位工作都变得容易控制。这样，使用者可专心于确认本身的设计问题，而不用花费时间去找到错误波形及分析。这会是个非常有效率的解决方案。   深圳市千兆科科技有限公司 0755-23062736 www.giga-science.com

Less than a decade ago, parallel buses were king and they were the primary means of moving information between systems, within systems and boards, and between components on a printed circuit board in a design. Now, high speed serial interconnects are dominant in almost every embedded systems design, from consumer and mobile devices to the high end routers and switches that power the wired Internet backbone. The range of designs that an embedded systems developer must be sure have reliable and high quality signal integrity over such interconnections range from car rear-view camera systems, where the data rate is usually less than 1Gbit/s to high-bandwidth Internet optical routers, where data rates are 10Gbps or more. Fortunately – or unfortunately depending on how you look at the problem—there are a number of different serial interconnect topologies and standard to help you, including SuperSpeed USB (Universal Serial Bus) 3.0, PCIe (Peripheral Component Interconnect Express), XAUI (10-Gbit attachment-unit interface), InfiniBand, RapidIO, and SATA (serial advanced-technology attachment) transmit data and clock signals using differential signals. And common to them all is the ubiquitous and ever useful serialiser/deserialiser (SERDES) interface that converts data signals back and forth between serial and parallel form. A commonality amongst such protocols is that the data transmitted embeds the clock, and the receiving system often uses 8b/10b encoding to provide a means of reliable clock extraction. Multilane implementations of these technologies bring further complexities. Four, eight, or more serial lanes carry signal components from transmitters to receivers, all with the goal of higher data throughput. In such topologies it can become a considerable challenge to hunt down and find even such mundane problems as a clock that intermittently outputs an incorrect duty cycle or a rise time that occasionally fails specifications. Adding to the challenge of ensuring signal integrity is that many of these complex high-speed serial buses use a variety of CDR (clock-data-recovery) techniques for data transmission or specilazed 8b/10b encoding schemes. Adding to the complexity of the problem is the trend towards multi-lane serial configurations. Facing such ongoing challenges in such designs requires that embedded developers continually educate themselves in all of the techniques and methodologies available. A good first step is to rely on web site resources where we are constantly adding to a knowledge base that has taken us a decade or more to create on the various serial design techniques available. These resources come in the form of design articles, technical papers and webinars, complemented with a range of relevant news and product stories. Because high speed serial interconnects will be with us for a long time, our goal is to continue to provide the most relevant design information available. For that we require your participation as well, in the form of blogs and design articles on serial interconnect design that you submit as well as your suggestions about the kind of content that would be most useful to you. I look forward to hearing from you.  

这篇文档详细讲解了10G或以上速率下，BGA fanout策略。 大概从以下方面来考虑： 1：可生产性      Via的选择，层叠的设置，走线的选择（背钻的可执行性） 2：信号完整性    线宽的选择，走线的insertion loss,return loss,crosstalk.