原创 SDI Design Challenges

Serial digital interface(SDI) is a standard for high quality lossless digital video transmission.

Depending on the data rate there are different variants of SDI:

- SD-SDI carries NTSC/PAL video data with a data rate of 270Mbps

- HD-SDI carries High Definition videos with a data rate of 1.485Gbps

- 3G-SDI carries 1080p50 videos with a data rate of 2.97Gbps

- Dual - Stream SDI carries two independent HD video streams in a single link. This results in a data rate of 2.97Gbps

The greatest advantage of SDI is being able to transfer high- definition video signals without any loss of quality. This is due to the fact that the video is transferred in uncompressed format. A video network based on SDI can be easily put together with a readily available 75 ohm co-axial cable between a transmitter and a receiver. Because of these benefits, SDI is rapidly becoming the leading video format for digital video transmission.

One of our recent designs involved an SDI transmit and receive, both working at 3G data rate. The scope of our project required that we output processed video streams on the SDI interface. We integrated a high-end video processor from TI along with a Spartan – 6 FPGA from Xilinx for this. The SDI physical interface was implemented by integrating an SDI core inside the FPGA. The SDI core mainly uses two clocks, one a Reference clock and  the other a pixel clock. The reference clock is a fixed LVDS clock input while the pixel clock is the one to which the parallel video data is synchronized from the processor. For proper functionality, SDI core expects both data and reference clocks to be in complete phase synchronization.

The main challenge that we faced in bringing up SDI-TX was in achieving synchronization between the processor’s pixel clock and the reference clock fed to the SDI core. To mitigate this, we added a FIFO in FPGA and used an internally generated clock inside the SDI core, as a FIFO read clock, with pixel clock being used as FIFO write clock. Although this resulted in phase synchronization, there were frequent underflow and overflow of FIFO due to minute frequency jitter among these clocks. To eliminate this, we had to find a common clock source for the pixel clock and the SDI core’s reference clock . To accomplish this, we connected a clock from FPGA, generated from SDI core reference clock, to an auxiliary clock input of the processor. Since the processor now derived the pixel clock using this auxiliary clock input, the FIFO overflow/underflow issue got resolved. Synchronization with the processor was not an issue for the SDI-RX path since the SDI-Core in itself generates pixel clock.

The second major problem that we encountered was with respect to Dual-stream SDI. To give DS-SDI output, SDI core requires two parallel video inputs which are frame synchronized. In our design, the processor was giving out two parallel video outputs to FPGA and it was not possible to achieve frame synchronization at the source. Thus, the FPGA had to align the two video frames before routing it to SDI core. Here we used a DDR3 connected to FPGA to achieve frame alignment. One of the incoming video stream data was written to DDR3 continuously beginning from the start of the frame, along with checking for start of frame in second video stream. Once the start-of-frame in second video data is detected, this stream along with the first stream, is sent to SDI core for generation of DS-SDI. The data from the first stream is not live in the sense that a stored frame is being read back from DDR3. It has to be noted that the size of the DDR3 memory must be big enough to store one complete frame.

The design of an SDI system not only involves proper understanding of the SDI core architecture but also careful high-speed design. In addition, a major aspect to getting the interface to work flawlessly is a robust PCB design. This becomes extremely important since the data rate in SDI line can go upto 2.97Gbps. The main objective of PCB layout design is to achieve uniform impedance along the entire trace. This included careful selection of series components on the trace, trace width selection, trace separation for differential lines etc. Since our design involved both SDI receive and transmit, we made sure that there was good enough separation between TX and RX circuits to avoid any interference.

- Suresha N S, Harshith Kasyap and Alagappan Ramanathan